AME8550 Datasheet, PDF (13/21 Pages) Analog Microelectronics – Voltage Detector

AME, Inc.
AME8550
Voltage Detector
n Functional Description
(CMOS output without delay)
1. When input voltage (V_DD) rises above detect voltage
(V_DF), output voltage (V_OUT) will be equal to V_DD.
( A condition of high impedance exists with Nch open
drain output configurations. )
2. When input voltage (V_DD) falls below detect voltage
(V_DF), output voltage (V_OUT) will be equal to the ground
voltage (V ) level.
SS
3. When input voltage (V_DD) falls to a level below that of
the minimum operating voltage (V_MIN), output will become
unstable. In this condition, V_DD will equal the pulled-up
output ( should output be pulled-up.)
4. When input voltage (V_DD) rises above the ground volt-
age (V ) level, output will be unstable at levels below the
SS
minimum operating voltage (V_MIN). Between the V_MIN and
detect release voltage (V_DR) levels, theground voltage (V_SS)
level will be maintained.
5. When input voltage (V ) rises above detect release
DD
voltage (V_DR), output voltage (V_OUT) will be equal to V_DD.
( A condition of high impedance exists with Nch open
drain output configurations. )
6. The difference between V_DR and V_DF represents the
hysteresis range.
n Timing Chart
6
Input Voltage (V_DD)
Detect Release Voltage (V_DR)
Detect Voltage (V_DF)
Min. Operating Voltage (V_MIN)
Ground Voltage (V_ss)
Output Voltage (V_OUT)
12
3
45
Ground Voltage (V_ss)
n Functional Description
(CMOS output with delay)
1. When input voltage (V_DD) rises above detect voltage
(V_DF), output voltage (V_OUT) will be equal to V_DD.
( A condition of high impedance exists with Nch open
drain output configurations. )
2. When input voltage (V_DD) falls below detect voltage
(V_DF), output voltage (V_OUT) will be equal to the ground
voltage (V ) level.
SS
3. When input voltage (V_DD) falls to a level below that of
the minimum operating voltage (V_MIN), output will become
unstable. In this condition, V_DD will equal the pulled-up
output ( should output be pulled-up.)
4. When input voltage (V_DD) rises above the ground volt-
age (V ) level, output will be unstable at levels below the
SS
minimum operating voltage (V_MIN). Between the V_MIN and
detect release voltage (V_DR) levels, theground voltage (V_SS)
level will be maintained.
5. When input voltage (V ) rises above detect release
DD
voltage (V_DR), output voltage (V_OUT) will be equal to V_DD
after T_D delay time.
Q = V x C = I x T_D
VxC
T=
I
V=V_REF
For
Example,
T_D=
V_REF * 1nF
75nA
( A condition of high impedance exists with Nch open
drain output configurations. )
6. The difference between V_DR and V_DF represents the
hysteresis range.
n Timing Chart
6
Input Voltage (V_DD)
Detect Release Voltage (V_DR)
Detect Voltage (V_DF)
Min. Operating Voltage (V_MIN)
Ground Voltage (V_ss)
Output Voltage (V_OUT)
T_D
12
3
45
Ground Voltage (V_ss)
13