AM29PLI60C Datasheet, PDF (9/44 Pages) Advanced Micro Devices – 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29PL160C Device Bus Operations
Read
Write
Operation
Standby
Output Disable
CE#
L
L
V_CC ±
0.3 V
L
OE#
L
H
X
H
WE#
H
L
X
H
Addresses
(Note 1)
A_IN
A_IN
X
X
DQ0–
DQ7
D_OUT
D_IN
High-Z
BYTE#
= V_IH
D_OUT
D_IN
High-Z
DQ8–DQ15
BYTE#
= V_IL
DQ8–DQ14 = High-Z,
DQ15 = A-1
High-Z
High-Z High-Z
High-Z
Legend:
L = Logic Low = V_IL, H = Logic High = V_IH, V_ID = 12.0 ± 0.5 V, X = Don’t Care, A_IN = Address In, D_IN = Data In, D_OUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V_IH), A19:A-1 in byte mode (BYTE# = V_IL).
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V_IL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V_IH. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array data
upon device power-up, or after a reset command
(when not executing a program or erase operation).
This ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 11 for the timing diagram. I_CC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Read Mode
Random Read (Non-Page Mode Read)
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is
the power control and should be used for device selec-
tion. OE# is the output control and should be used to
gate data to the output pins if the device is selected.
Address access time (t_ACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t_CE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
t_ACC–t_OE time).
8
Am29PL160C
June 12, 2002