AM79C961 Datasheet, PDF (89/173 Pages) Advanced Micro Devices – PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA

PRELIMINARY
AMD
Register by issuing increment
commands to increment the
memory address for sequential
operations. The DMABA register
is undefined until the first
PCnet-ISA⁺ controller DMA
operation.
This register has meaning only if
the PCnet-ISA⁺ controller is in
Bus Master Mode.
Read/write accessible only when
STOP bit is set.
CSR86: Buffer Byte Counter
Bit Name
Description
15-12 RES
11-0 DMABC
Reserved, Read and written with
ones.
DMA Byte Count Register. Con-
tains the Two’s complement of
the current size of the remaining
transmit or receive buffer in
bytes. This register is incre-
mented by the Bus Interface Unit.
The DMABC register is unde-
fined until written.
Read/write accessible only when
STOP bit is set.
CSR88-89: Chip ID
Bit Name
Description
31-28
27-12
11-1
0
Version. This 4-bit pattern is sili-
con revision dependent.
Part number. The 16-bit code for
the PCnet-ISA⁺ controller is
0010001001100000b.
Manufacturer ID. The 11-bit
manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
Always a logic 1.
This register is exactly the same
as the Chip ID register in the
JTAG description.
CSR92: Ring Length Conversion
Bit Name
Description
15-0 RCON
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an en-
coded value as found in the
initialization block to a Two’s
complement value used for inter-
nal counting. By writing bits
15–12 with an encoded ring
length, a Two’s complemented
value is read. The RCON register
is undefined until written.
Read/write accessible only when
STOP bit is set.
CSR94: Transmit Time Domain Reflectometry
Count
Bit Name
Description
15-10 RES
9-0 XMTTDR
Reserved locations. Read and
written as zero.
Time Domain Reflectometry re-
flects the state of an internal
counter that counts from the start
of transmission to the occurrence
of loss of carrier. TDR is incre-
mented at a rate of 10 MHz.
Read accessible only when
STOP bit is set. Write operations
are ignored. XMTTDR is cleared
by RESET.
CSR96-97: Bus Interface Scratch Register 0
Bit Name
Description
31-0 SCR0
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers. The SCR0
register is undefined until written.
Read/write accessible only when
STOP bit is set.
CSR98-99: Bus Interface Scratch Register 1
Bit Name
Description
31-0 SCR1
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers.
Read/write accessible only when
STOP bit is set.
CSR104-105: SWAP
Bit Name
Description
31-0 SWAP
This register performs word and
byte swapping depending upon if
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