AM85C30 Datasheet, PDF (67/68 Pages) Advanced Micro Devices – Enhanced Serial Communications Controller

AMD
AMENDMENT
SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range
(continued)
Interrupt Acknowledge Timing, Reset Timing, Cycle Timing (see Figures 22–24)
Parameter
No. Symbol
Parameter
Description
8.192 MHz
10 MHz
16.384 MHz
20 MHz
Industrial Only
Min Max Min Max Min Max Min Max Unit
27 TdA(DR)
Address Required Valid to Read
Data Valid Delay
28 TwWRI
WR Low Width
29 TdWRf(DW)
WR ↓ to Write Data Valid
30 ThDW(WR)
Write Data to WR ↑ Hold Time
31 TdWR(W)
WR ↓ to Wait Valid Delay (Note 2)
32 TdRD(W)
RD ↓ to Wait Valid Delay (Note 2)
33 TdWRf(REQ) WR ↓ to W/REQ Not Valid Delay
34 TdRDf(REQ) RD ↓ to W/REQ Not Valid Delay
35a TdWRr(REQ) WR ↓ to DTR/REQ Not Valid Delay
35b TdWRr(EREQ) WR ↓ to DTR/REQ Not Valid Delay
36 TdRDr(REQ) RD ↑ to DTR/REQ Not Valid Delay
37 TdPC(INT)
PCLK ↓ to INT Valid Delay (Note 2)
38 TdIAi(RD)
INTACK to RD ↓ (Acknowledge)
Delay (Note 3)
39 TwRDA
RD (Acknowledge) Width
40 TdRDA(DR)
RD ↓ (Acknowledge) to Read
Data Valid Delay
41 TsIEI(RDA)
IEI to RD ↓ (Acknowledge) Setup
Time
42 ThIEI(RDA)
IEI to RD ↑ (Acknowledge) Hold
Time
43 TdIEI(IEO)
IEI to IEO Delay Time
44 TdPC(IEO)
PCLK ↑ to IEO Delay
45 TdRDA(INT) RD ↓ to INT Inactive Delay (Note 2)
46 TdRD(WRQ) RD ↑ to WR ↓ Delay for No Reset
47 TdWRQ(RD) WR ↑ to RD ↓ Delay for No Reset
48 TwRES
WR and RD Coincident Low for
Reset
49 Trc
Valid Access Recovery Time
(Note 1)
220
160
100
90 ns
150
125
75
65
ns
35
35
20
20 ns
0
0
0
0
ns
170
100
50
50 ns
170
100
50
50 ns
170
120
70
65 ns
170
120
70
65 ns
4TcPc
4TcPc
4TcPc
4TcPc ns
120
120
70
65 ns
NA
NA
NA
NA ns
500
400
175
160 ns
150
125
50
45
ns
150
125
75
65
ns
140
120
70
60 ns
95
80
50
45
ns
0
0
0
0
ns
95
80
45
40 ns
200
175
80
70 ns
450
320
200
180 ns
15
15
10
10
ns
15
15
10
10
ns
150
100
75
65
ns
3.5
3.5
3.5
3.5
TcPc
Notes:
1 Parameter applies only between transactions involving the ESCC, if WR/RD falling edge is synchronized to PCLK
falling edge, then TrC = 3TcPc.
2. Open-drain output, measured with open-drain test load.
3. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of DdPC(IEO)
for the highest priority device in the daisy chain, TsIEI(RDA) for the SCC, and TdIEI(IEO) for each device separating
them in the daisy chain.
4. Parameter applies to Enhanced Request mode only.
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Am85C30