AMSN2800DUT4C Datasheet, PDF (47/102 Pages) Advanced Micro Devices – Processor Model 10 Multiprocessor Platforms

26426C—October 2003
Preliminary Information
AMD Athlon™ MP Processor Model 10 Data Sheet for Multiprocessor Platforms
7.11
General AC and DC Characteristics
Table 12 shows the AMD Athlon MP processor model 10 AC and
DC characteristics of the Southbridge, JTAG, test, and
miscellaneous pins.
Table 12. General AC and DC Characteristics
Symbol
Parameter Description
Condition
Min
Max
Units Notes
V_IH
Input High Voltage
(V_{CC_CORE} / 2) + V_{CC_CORE} +
V
1, 2
200 mV
300 mV
V_IL
Input Low Voltage
–300
350
mV 1, 2
V_OH
Output High Voltage
V_{CC_CORE} –
400
V_{CC_CORE} + _mV
300
V_OL
Output Low Voltage
–300
400
mV
I_{LEAK_P} Tristate Leakage Pullup
V_IN = VSS
–1
(Ground)
mA
I_{LEAK_N Tristate Leakage Pulldown}
V_IN = V_{CC_CORE}
Nominal
600
µA
I_OH
Output High Current
–6
mA 3
I_OL
Output Low Current
6
mA 3
T_SU
Sync Input Setup Time
2.0
ns 4, 5
T_HD
Sync Input Hold Time
0.0
ps 4, 5
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal V_{CC_CORE} . Scale parameters between V_{CC_CORE.} minimum and V_{CC_CORE.} maximum.
3. I_OL and I_OH are measured at V_OL maximum and V_OH minimum, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more
information.
Chapter 7
Electrical Data
35