DS42546 Datasheet, PDF (40/57 Pages) Advanced Micro Devices – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

AC CHARACTERISTICS
Flash Erase and Program Operations
Parameter
JEDEC
Std Description
t_AVAV
t_AVWL
t_WC Write Cycle Time (Note 1)
t_AS Address Setup Time (WE# to Address)
t_ASO
Address Setup Time to OE# or CE#f low during toggle bit
polling
t_WLAX
t_AH Address Hold Time (WE# to Address)
t_AHT
Address Hold Time From CE#f or OE# high during toggle bit
polling
t_DVWH
t_WHDX
t_DS Data Setup Time
t_DH Data Hold Time
t_OEH OE# Hold Time
Read
Toggle and Data# Polling
t_GHEL
t_GHWL
t_WLEL
t_ELWL
t_EHWH
t_WHEH
t_WLWH
t_ELEH
t_WHDL
t_WHWH1
t_OEPH
t_GHEL
t_GHWL
t_WS
t_CS
t_WH
t_CH
t_WP
t_CP
t_WPH
t_SR/W
t_WHWH1
Output Enable High during toggle bit polling
Read Recovery Time Before Write (OE# High to CE#f Low)
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time (CE#f to WE#)
CE#f Setup Time (WE# to CE#f)
WE# Hold Time (CE#f to WE#)
CE#f Hold Time (CE#f to WE#)
Write Pulse Width
CE#f Pulse Width
Write Pulse Width High
Latency Between Read and Write Operations
Programming Operation (Note 2)
Byte
Word
t_WHWH1
t_WHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
t_WHWH2
t_WHWH2 Sector Erase Operation (Note 2)
t_VCS V_CCf Setup Time (Note 1)
t_RB Write Recovery Time from RY/BY#
t_BUSY Program/Erase Valid to RY/BY# Delay
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
85 ns Speed
Min
Typ
Max
85
0
15
45
0
35
0
0
10
20
20
20
0
0
0
0
0
0
35
35
30
0
5
7
4
0.7
50
0
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
sec
µs
ns
ns
40
DS42546