AM41PDS3224D Datasheet, PDF (39/59 Pages) Advanced Micro Devices – 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM

PRELIMINARY
FLASH AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Option
JEDEC Std Description
Test Setup
10
11 Unit
t_AVAV
t_RC Read Cycle Time (Note 1)
Min 100 110 ns
t_AVQV
t_ACC Address to Output Delay
CE#, OE# = V_IL Max
100
110
ns
t_PRC Page Read Cycle
Min
40
45
ns
t_PACC Page Address to Output Delay
CE#, OE# = V_IL Max
40
45
ns
t_ELQV
t_CE Chip Enable to Output Delay
OE# = V_IL
Max 100 110 ns
t_GLQV
t_OE Output Enable to Output Delay
Max
35
45
ns
t_EHQZ
t_DF Chip Enable to Output High Z (Notes 1, 3)
Max
16
ns
t_GHQZ
t_DF Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
t_AXQX
t_OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
t_OEH
Output Enable Hold
Time (Note 1)
Read
Toggle and
Data# Polling
Min
0
ns
Min
10
ns
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
3. Measurements performed by placing a 50Ω termination on the data pin with a bias of V_CC/2. The time from OE# high to the
data bus driven to V_CC/2 is taken as t_DFAC Characteristics.
Addresses
CE#f
OE#
WE#
Outputs
RESET#
RY/BY# _{0 V}
t_RC
Addresses Stable
t_ACC
t_RH
t_RH
t_OEH
HIGH Z
t_OE
t_CE
t_DF
t_OH
Output Valid
Figure 15. Conventional Read Operation Timings
HIGH Z
38
Am41PDS3224D
May 13, 2002