DS42515 Datasheet, PDF (35/57 Pages) Advanced Micro Devices – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

TEST CONDITIONS
3.3 V
Device
Under
Test
C_L
6.2 kΩ
2.7 kΩ
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Table 14. Test Specifications
Test Condition
85 ns
Unit
Output Load
1 TTL gate
Output Load Capacitance, C_L
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
Input Pulse Levels
0.0–3.0
V
Input timing measurement reference
levels
1.5
V
Output timing measurement
reference levels
1.5
V
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
Steady
OUTPUTS
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
3.0 V
0.0 V
Input
1.5 V
Measurement Level
1.5 V
Figure 12. Input Waveforms and Measurement Levels
Output
DS42515
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