PAL16L8B Datasheet, PDF (33/33 Pages) Advanced Micro Devices – 20-Pin TTL Programmable Array Logic

POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will be HIGH due to the inverting output
buffer. This feature is valuable in simplifying state
machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous opera-
tion of the power-up reset and the wide range of ways
Parameter
Symbol
tPR
tS
tWL
Parameter Description
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
AMD
VCC can rise to its steady state, two conditions are
required to ensure a valid power-up reset. These condi-
tions are:
s The VCC rise must be monotonic.
s Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feed-
back setup times are met.
Max
Unit
1000
ns
See Switching
Characteristics
Power
Registered
Active-Low
Output
Clock
4V
tPR
tS
tWL
VCC
16492D-31
Power-Up Reset Waveform
PAL16R8 Family
2-35