AM79C970 Datasheet, PDF (29/168 Pages) Advanced Micro Devices – PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus

AMD
PRELIMINARY
Target Abort
Figure 9 shows a target abort sequence. The target as-
serts DEVSEL for one clock. It then deasserts DEVSEL
and asserts STOP on clock 4. A target can use the target
abort sequence to indicate that it cannot service the data
transfer and that it does not want the transaction to be
retried. Additionally, the PCnet-PCI controller cannot
make any assumption about the success of the previous
data transfers in the current transaction. The PCnet-PCI
controller terminates the current transfer with the
deassertion of FRAME on clock 5 and one clock cycle
later with the deassertion of IRDY. It finally releases the
bus on clock 6.
Since data integrity is not guaranteed, the PCnet-PCI
controller cannot recover from a target abort event. The
PCnet-PCI controller will reset all CSR and BCR loca-
tions to their H_RESET values. Any on-going network
activity will be stopped immediately. The PCI configura-
tion registers will not be cleared. RTABORT (bit 12) in
the Status register will be set to indicate that the PCnet-
PCI controller has received a target abort.
CLK
1
2
3
4
5
6
FRAME
AD
ADDR DATA
C/BE
0111
0000
PAR
PAR PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
DEVSEL is sampled by the PCnet-PCI controller.
18220C-11
Figure 9. Target Abort
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Am79C970