AM29DL320G Datasheet, PDF(28/58 Page) SPANSION – For new designs involving TSOP packages, S29JL032H supercedes Am29DL320G and is the factory-recommended migration path.

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AM29DL320G Datasheet, PDF (28/58 Pages) SPANSION – For new designs involving TSOP packages, S29JL032H supercedes Am29DL320G and is the factory-recommended migration path.

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VHH on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at VHH any operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

Figure 4 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 18 for timing diagrams.

START

Write Program

Command Sequence

Embedded

Program

algorithm

in progress

Data Poll

from System

Verify Data?

Yes

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 13 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 13

shows the address and data requirements for the chip

erase command sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Write Operation Status sec-

tion for information on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 20 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 13 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 Âµs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands (for sectors within the same bank) may be writ-

ten. Loading the sector erase buffer may be done in

any sequence, and the number of sectors may be from

one sector to all sectors. The time between these ad-

ditional cycles must be less than 50 Âµs, otherwise era-

sure may begin. Any sector erase address and

command following the exceeded time-out may or may

not be accepted. It is recommended that processor in-

terrupts be disabled during this time to ensure all com-

mands are accepted. The interrupts can be re-enabled

after the last Sector Erase command is written. Any

command other than Sector Erase or Erase Sus-

Am29DL320G

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