AM79C864A Datasheet, PDF (27/51 Pages) Advanced Micro Devices – Physical Layer Controller With Scrambler (PLC-S)

PRELIMINARY
AMD
INTR_EVENT register is set whenever the counter
increments or whenever the counter overflows (reaches
256), depending on the setting of the
VSYM_CTR_INTRS bit in the PLC_CNTRL_A register.
When the counter overflows it wraps to zero and contin-
ues to count.
The Violation Symbol Counter is incremented whenever
the 4B/5B decoder in the PLC-S decodes a violation
symbol. See the Decoder description for the symbols
considered to be violation symbols by the Decoder.
They are represented as a “V” in Table 15.
Minimum Idle Counter (MIN_IDLE_CTR)
The Minimum Idle Counter has address 19 (hex). It is
read-only and is cleared whenever it is read as well as
when RST is asserted. The high order 9 bits of the regis-
ter will always be read as zeros.
Bits 6 through 4 of the counter contain the value in the
Idle Counter Minimum Detector. This is the minimum
number of inter-packet Idle symbol pairs seen since the
counter was last reset. It gets reset to 7. Whenever the
value changes to a lower value, the MINI_CTR bit in the
INTR_EVENT register is set. The Idle symbol pair count
definitions are given in Table 8.
Table 8. Idle Counter Minimum Detector
MIN_IDLE_CTR 6–4
100
101
111
110
010
011
001
000
Idle Symbol Pair Count
7 or more
6
5
4
3
2
1
0
Bits 3 through 0 of the counter contain the value in the
Minimum Idle Gap Counter. This is the number of times
the minimum number of inter-packet Idles has been
seen since the last reset. It gets reset to 1. The
MINI_CTR bit in the INTR_EVENT register is set when-
ever the counter increments or whenever the counter
overflows (reaches 16), depending on the setting of the
MINI_CTR_INTRS bit in the PLC_CNTRL_A register.
When the counter overflows, it remains at 16. The mini-
mum Idle occurrence count definitions are given in
Table 9.
Table 9. Minimum Idle Gap Counter
MIN_IDLE_CTR 3–0
0000
1000
1100
0100
0101
0111
1111
1110
1010
0010
0011
0001
1001
1101
0110
1011
Minimum Idle
Occurrence Count
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Link Error Event Counter (LINK_ERR_CTR)
The Link Error Event Counter has address 1A (hex). It is
read-only and is cleared whenever it is read as well as
when RST is asserted. It is an 8-bit counter contained in
bits 7 through 0 of the register. Bits 15 through 8 of the
register will always be read as zeros. The LE_CTR bit in
the INTR_EVENT register is set whenever the counter
reaches the value contained in the LE_THRESHOLD
register. The counter will continue to count past this
point. When the counter overflows (reaches 256), it
wraps to zero and continues to count.
The Link Error Event Counter is part of the Link Error
Monitor (LEM) and is implemented in the PLC-S. The
LEM monitors Bit Error Rate (BER) of an active link and
detects and isolates physical links having an inadequate
BER, e.g. due to a marginal link quality, link degradation
or connector unplugging.
In addition to the counter, the PLC-S also contains logic
to detect link error events. Link error events are defined
in Table 12.
Am79C864A
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