AM79C875 Datasheet, PDF (23/48 Pages) Advanced Micro Devices – NetPHY™ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver

PHY Control and Management Block
(PCM Block)
Register Administration for 100BASE-X PHY
Device
The management interface specified in Clause 22 of
the IEEE 802.3u standard provides for a simple two
wire, serial interface to connect a management entity
and a managed PHY for the purpose of controlling the
PHY and gathering status information. The two lines
are Management Data Input/Output (MDIO) and
Management Data Clock (MDC). A station manage-
ment entity which is attached to multiple PHY entities
must have prior knowledge of the appropriate PHY ad-
dress for each PHY entity.
Description of the Methodology
The management interface physically transports man-
agement information across the RMII. The information
is encapsulated in a frame format as specified in
Clause 22 of IEEE 802.3u draft standard and is shown
in Table 3.
Table 3. Clause 22 Management Frame Format
PRE
ST
OP
PHYAD
REGADD
TA
DATA
IDLE
READ
1.1
01
10
AAAAA
RRRRR
Z0
D...........D
Z
WRITE
1.1
01
01
AAAAA
RRRRR
10
D...........D
Z
The PHYAD field, which is five bits wide, allows 32
unique PHY addresses. The managed PHY layer de-
vice that is connected to a station management entity
via the MII interface has to respond to transactions
addressed to the PHY's address. A station manage-
ment entity attached to multiple PHYs, such as in a
managed 802.3 Repeater or Ethernet switch, is re-
quired to have prior knowledge of the appropriate PHY
address.
Setting the PHYAD Bits
The PHYAD of each port is the combination of the set-
ting of the NetPHY™ 4LP device and the port number.
The NetPHY™ 4LP device is set by PHYAD[4:2] at the
rising edge of RST. The lower two bits of the PHYAD
are set by the individual ports in the PHY. If the
PHYAD[4:2] is set to 010, the PHYAD of each port is as
follows:
Port 0
Port 1
Port 2
Port 3
01000
01001
01010
01011
Section 22 of the IEEE 802.3 standard states that all
PHY devices connected to a mechanical interface will
respond to PHYAD “00000” command regardless of
the actual address of the PHY. There are applications
where it is necessary to avoid setting the PHYAD of a
port to “00000.” The NetPHY™ 4LP contains a mecha-
nism that allows the PHYADs to be shifted by 1. The
PHYAD_ST pin enables this mechanism. If the pin is
LOW at power-up, the PHYADs are incremented by 1.
To set the PHYAD pins, use pull-up or pull-down resis-
tors in the range of 1 KΩ to 4.7 KΩ.
If PHYAD is set to 000, the address of each port is as
follows:
Port 0
00001
Port 1
00010
Port 2
00011
Port 3
00100
The address shifting carries over the entire address
space. If PHYAD[4:2] is set to 111, the PHYAD for each
port is as follows:
Port 0
Port 1
Port 2
Port 3
11101
11110
11111
00000
Table 4. PHY Address Setting Frame Structure
PRE ST OP
PHYAD
REGADD
TA
DATA
READ
1.1
01 10
00000
RRRRR
Z0
XXXXXXXXXPPAAAAA
WRITE
1.1
01 01
00000
RRRRR
10
XXXXXXXXXPPAAAAA
IDLE
Z
Z
Am79C875
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