AM79C973 Datasheet, PDF (149/304 Pages) Advanced Micro Devices – PCnet™-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY

PRELIMINARY
CSR67: Next Transmit Status
Bit Name
Description
31-16 RES
15-0 NXST
Reserved locations. Written as
zeros and read as undefined.
Next Transmit Status. This field is
a copy of bits 31-16 of TMD1 of
the next transmit descriptor.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
7-0 RES
Reserved locations. Read and
written as zeros. Accessible only
when either the STOP or the
SPND bit is set.
CSR72: Receive Ring Counter
Bit Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 RCVRC
Receive Ring Counter location.
Contains a two’s complement bi-
nary number used to number the
current receive descriptor. This
counter interprets the value in
CSR76 as pointing to the first de-
scriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR74: Transmit Ring Counter
Bit Name
Description
31-16 RES
15-0 XMTRC
Reserved locations. Written as
zeros and read as undefined.
Transmit Ring Counter location.
Contains a two’s complement bi-
nary number used to number the
current transmit descriptor. This
counter interprets the value in
CSR78 as pointing to the first de-
scriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR76: Receive Ring Length
Bit Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 RCVRL
Receive Ring Length. Contains
the two’s complement of the re-
ceive descriptor ring length. This
register is initialized during the
Am79C973/Am79C975 controller
initialization routine based on the
value in the RLEN field of the ini-
tialization block. However, this
register can be manually altered.
The actual receive ring length is
defined by the current value in
this register. The ring length can
be defined as any value from 1 to
65535.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR78: Transmit Ring Length
Bit Name
Description
31-16 RES
15-0 XMTRL
Reserved locations. Written as
zeros and read as undefined.
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the
Am79C973/
Am79C975Am79C973/
Am79C975 controller initializa-
tion routine based on the value in
the TLEN field of the initialization
block. However, this register can
be manually altered. The actual
transmit ring length is defined by
the current value in this register.
The ring length can be defined as
any value from 1 to 65535.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
Am79C973/Am79C975
149