AM79C970A Datasheet, PDF (142/219 Pages) Advanced Micro Devices – PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product

AMD
13–9 RES
8 APROMWE
7 INTLEVEL
PRELIMINARY
Read/Write accessible always.
TMAULOOP is cleared to ZERO
by H_RESET and is unaffected
by S_RESET or by setting the
STOP bit.
Reserved locations. Written as
ZEROs and read as undefined.
Address PROM Write Enable.
The PCnet-PCI II controller con-
tains a shadow RAM on board
for storage of the first 16
bytes loaded from the serial
EEPROM. Accesses to Address
PROM I/O Resources will be
directed toward this RAM. When
APROMWE is set to ONE, then
write access to the shadow RAM
will be enabled.
Read/Write accessible always.
APROMWE is cleared to ZERO
by H_RESET and is unaffected
by S_RESET or by setting the
STOP bit.
Interrupt Level. This bit allows
the interrupt output signals to be
programmed for level or edge-
sensitive applications.
When INTLEVEL is cleared to
ZERO, the INTA pin is configured
for level-sensitive applications.
In this mode, an interrupt request
is signaled by a low level
driven on the INTA pin by the
PCnet-PCI II controller. When
the interrupt is cleared, the INTA
pin is tri-stated by the PCnet-PCI
II controller and allowed to be
pulled to a high level by an exter-
nal pullup device. This mode is
intended for systems which allow
the interrupt signal to be shared
by multiple devices.
When INTLEVEL is set to ONE,
the INTA pin is configured for
edge-sensitive applications. In
this mode, an interrupt request is
signaled by a high level driven on
the INTA pin by the PCnet-PCI II
controller. When the interrupt is
cleared, the INTA pin is driven to
a low level by the PCnet-PCI II
controller. This mode is intended
for systems that do not allow in-
terrupt channels to be shared by
multiple devices.
6
RES
5 DXCVRCTL
4 DXCVRPOL
INTLEVEL should not be set to
ONE when the PCnet-PCI II
controller is used in a PCI
bus application.
Read/Write accessible always.
INTLEVEL is cleared to ZERO by
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
Reserved location. Written as
ZERO and read as undefined.
DXCVR Control. When the AUI
or GPSI interface is the active
network port, DXCVRCTL con-
trols the assertion of the DXCVR
output. The polarity of the as-
serted state is controlled by the
DXCVRPOL bit (BCR2, bit 4).
The DXCVR pin can be used to
control a DC-to-DC converter in
applications that want to connect
a 10BASE2 MAU as well as a
standard DB15 AUI connector to
the PCnet-PCI II controller AUI or
GPSI port. When DXCVRCTL is
set to ONE, the DXCVR output
will be asserted. This could be
used to enable a DC-to-DC con-
verter for 10BASE2 MAUs (as-
suming the enable input of the
DC-to-DC converter is active
high and DXCVRPOL is cleared
to ZERO). When DXCVRCTL is
cleared to ZERO, the DXCVR
output will be deasserted. This
would power down the DC-to-DC
converter. When the 10BASE-T
interface is the active network
port, the DXCVR output is
always deasserted.
Read/Write accessible always.
DXCVRCTL is cleared by
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
DXCVR Polarity. This bit controls
the polarity of the asserted state
of the DXCVR output. When
DXCVRPOL is cleared to ZERO,
the DXCVR output will be
HIGH when asserted. When
DXCVRPOL is set to ONE, the
DXCVR output will be LOW
when asserted.
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Am79C970A