AM79C960 Datasheet, PDF (116/127 Pages) Advanced Micro Devices – PCnetTM-ISA Single-Chip Ethernet Controller

AMD
PRELIMINARY
SWITCHING WAVEFORMS: GPSI
Transmit
Clock
(STDCLK)
Transmit
Data
(TXDAT)
(First Bit Preamble)
tGPT1
tGPT2
tGPT3
tGPT3
Transmit
Enable
(TXEN)
Carrier
Present
(RXCRS)
(Note 1)
tGPT9
(Last Bit )
tGPT3
tGPT4
tGPT6
Collision
(CLSN)
(Note 2)
tGPT7
tGPT5
tGPT8
Notes:
1. If RXCRS is not present during transmission, LCAR bit in TMD3 will be set.
2. If CLSN is not present during or shortly after transmission, CERR in CSR0 will be set.
Transmit Timing
Receive
Clock
(SRDCLK)
Receive
Data
(RXDAT)
Carrier
Present
(RXCRS)
Collision
(CLSN),
Active
Collision
(CLSN),
Inactive
(First Bit Preamble)
tGPR1
tGPR2
tGPR4
tGPR4
tGPR5
tGPR11
tGPR7
tGPR3
(Address Type Designation Bit) (Last Bit)
tGPR5
tGPR8
tGPR6
tGPR9
tGPR10
(No Collision)
tGPR12
16907B-63
16907B-64
Receive Timing
1-458
Am79C960