AM79C961A_00 Datasheet, PDF (112/206 Pages) Advanced Micro Devices – PCnet™-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA

CSR96-97: Bus Interface Scratch Register 0
Bit Name
Description
CSR108-109: Buffer Management Scratch
Bit Name
Description
31-0 SCR0
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All
Descriptor Data communica-
tions between the BIU and BMU
are written and read through
SCR0 and SCR1 registers. The
SCR0 register is undefined until
written.
Read/write accessible only when
STOP or SPND bits are set.
CSR98-99: Bus Interface Scratch Register 1
Bit Name
Description
31-0 SCR1
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All
Descriptor Data communica-
tions between the BIU and BMU
are written and read through
SCR0 and SCR1 registers.
Read/write accessible only
when STOP or SPND bits are
set.
CSR104-105: SWAP
Bit Name
Description
31-0 SWAP
This register performs word and
byte swapping depending upon
if 32-bit or 16-bit internal write
operations are performed. This
register is used internally by the
BIU/BMU as a word or byte
swapper. The swap register can
perform 32-bit operations that
the PC can not; the register is
externally accessible for test
reasons only. CSR104 holds the
lower 16 bits and CSR105 holds
the upper 16 bits.
The swap function is defined as
follows:
Internal Write Operation SWAP Register Result
32-Bit word
Lower 16-Bit
(CSR104)
SRC[31:16]→SWAP[15:0]
SRC[15:0]→SWAP[31:16]
SRC[15:8]→SWAP[7: 0]
SRC[7:0]→SWAP[15:8]
Read/write accessible only
when STOP or SPND bits are
set.
31-0 BMSCR
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status.
This register is also used as the
primary scan register for Buffer
Management Test Modes.
BMSCR register is undefined
until written.
Read/write accessible only
when STOP bit is set.
CSR112: Missed Frame Count
Bit Name
Description
15-0 MFC
Counts the number of missed
frames.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When MFC is all 1’s (65535) and
a missed frame occurs, MFC
increments to 0 and sets MFC0
bit (CSR4.9).
CSR114: Receive Collision Count
Bit Name
Description
15-0 RCVCC
Counts the number of Receive
collisions seen, regular and late.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When RCVCC is all 1’s (65535)
and a receive collision occurs,
RCVCC increments to 0 and
sets RCVCC0 bit (CSR4.5)
CSR124: Buffer Management Unit Test
Bit Name
Description
15-5 RES
4 GPSIEN
This register is used to place the
BMU/BIU into various test
modes to support Test/Debug.
This register is writeable when
the ENTST bit in CSR4 is set.
Reserved locations. Written as
zero and read as undefined.
This mode places the PCnet-ISA
II controller in the GPSI Mode.
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Am79C961A