AM29F400AT Datasheet, PDF (1/35 Pages) Advanced Micro Devices – 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory

PRELIMINARY
Am29F400AT/Am29F400AB
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
s Compatible with JEDEC-standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s Package options
— 44-pin SO
— 48-pin TSOP
s Minimum 100,000 write/erase cycles guaranteed
s High performance
— 60 ns maximum access time
s Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
seven 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
s Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
s Embedded Erase™ Algorithms
— Automatically preprograms and erases the chip
or any sector
GENERAL DESCRIPTION
The Am29F400A is a 4 Mbit, 5.0 Volt-only Flash memory
organized as 512 Kbytes of 8 bits each or 256 Kwords
of 16 bits each. The 4 Mbits of data is divided into 11
sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte,
and seven 64 Kbytes, for flexible erase capability. The
8 bits of data will appear on DQ0–DQ7 or 16 bits on
DQ0–DQ15. The Am29F400A is offered in 44-pin SO
and 48-pin TSOP packages. This device is designed
to be programmed in-system with the standard system
5.0 Volt V_CC supply. 12.0 Volt V_PP is not required for
program or erase operations. The device can also be re-
programmed in standard EPROM programmers.
s Embedded Program™ Algorithms
— Automatically programs and verifies data at
specified address
s Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
s Ready/Busy output (RY/BY)
— Hardware method for detection of program or
erase cycle completion
s Erase Suspend/Resume
— Supports reading data from a sector not being
erased
s Low power consumption
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
s Enhanced power management for standby
mode
— 1 µA typical standby current
s Boot Code Sector Architecture
— T = Top sector
— B = Bottom sector
s Hardware RESET pin
— Resets internal state machine to the read mode
The standard Am29F400A offers access times of
60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has sepa-
rate chip enable (CE), write enable (WE) and output
enable (OE) controls.
The Am29F400A is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine
which controls the erase and programming circuitry.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 20380 Rev: B Amendment/0
Issue Date: April 1997