440GX Datasheet, PDF (84/93 Pages) Applied Micro Circuits Corporation – Power PC 440GX Embedded Processor

440GX – Power PC 440GX Embedded Processor
DDR SDRAM MemClkOut0 and Read Clock Delay
PLB Clk
Revision 1.15 – August 30, 2007
Data Sheet
MemClkOut0(0)
T_MD
T_MDmin = 567ps
T_MDmax = _1705ps
Read Clock
T_RD
T_RDmin = -6 ps
T_RDmax = 183ps
In operation, following the receipt of an address and read command from the PPC440GX, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GX using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
Package pins
Stage 1
Stage 2
Stage 3
Mux
RDSP
D
Q
ECC
FF
PLB bus
Data
D
Q
FF,
D
Q
FF
D
Q
FF
C
XL
DQS
1/4
Cycle
Delay
C
C
Programmed
Read Clock
Delay
C
Read Select
(SDRAM0_TR1)
PLB Clock
FF Timing:
T_IS = Input setup time = 0.2ns
T_IH = Input hold time = 0.1ns
T_P = Propagation delay (D to Q or C to Q) = 0.4ns maximum
FF: Flip-Flop
XL: Transparent Latch
84
AMCC