440GR Datasheet, PDF (78/82 Pages) Applied Micro Circuits Corporation – Power PC 440GR Embedded Processor

Revision 1.16 – July 19, 2006
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system
will still work, but there will be more latency before the data is sampled into RDSP. In this example, T_T and T_TE are
controlled and set by the software.
Figure 13. DDR SDRAM Read Cycle Timing—Example 3
DQS at pin
Data at pin
D0
D1
D2
D3
DQS Stage 1 C
T_SIN
Data in Stage 1 D
T_DIN
Data out Stage 1
D0
T_P
High
Low
D1
D0
D0 D1
D2
D3
D2
D2
D3
PLB Clock
Read Clock Delayed
T_P
High
Data out Stage 2
Low
Data out Stage 3
with ECC
High
Low
Data in at RDSP
with ECC
High
Low
D0
D2
D1
D3
D0
D1
T_TE
D2
D3
D0
D1
High
D0
Data out RDSP
with ECC
Low
D1
(3)
T_T = Propagation delay from Stage 2 input to RDSP input w/o ECC
T_TE = Propagation delay from Stage 2 input to RDSP input with ECC
D2
D3
D2
D3
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