440GRX Datasheet, PDF (77/88 Pages) Applied Micro Circuits Corporation – PowerPC 440GRx Embedded Processor

Revision 1.08 – October 15, 2007
Preliminary Data Sheet
440GRx – PPC440GRx Embedded Processor
Table 21. I/O Specifications—All Speeds (Sheet 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
Ethernet RGMII Interface
GMC0RxClk
GMC0TxClk
GMC0RxD0:3
1
1
GMC0RxCtl
1
1
GMC0TxD0:3
n/a
n/a
GMC0TxCtl
n/a
n/a
GMC1RxClk
GMC1TxClk
GMC1RxD0:3
1
1
GMC1RxCtl
1
1
GMC1TxD0:3
n/a
n/a
GMC1TxCtl
n/a
n/a
GMCRefClk
Ethernet SMII Interface
SMIIRefClk
SMIISync
na
na
SMII0RxD
1.5
1
SMII1RxD
1.5
1
SMII0TxD
n/a
n/a
SMII1TxD
n/a
n/a
Internal Peripheral Interface
IIC0SClk
IIC0SData
n/a
n/a
IIC1SClk
IIC1SData
n/a
n/a
SCPClkOut
SCPDI
5
1.5
SCPDO
n/a
n/a
UARTSerClk
UARTn_Rx
n/a
n/a
UARTn_Tx
n/a
n/a
UARTn_DCD
n/a
n/a
UARTn_DSR
n/a
n/a
UARTn_CTS
n/a
n/a
UARTn_DTR
n/a
n/a
UARTn_RI
n/a
n/a
UARTn_RTS
n/a
n/a
Interrupts Interface
IRQ0:9
n/a
n/a
JTAG Interface
TCK
n/a
n/a
TDI
n/a
n/a
TDO
n/a
n/a
TMS
n/a
n/a
TRST
n/a
n/a
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
n/a
n/a
n/a
n/a
0.5
3.5
0.5
3.5
n/a
n/a
n/a
n/a
0.5
3.5
0.5
3.5
3
1
n/a
n/a
n/a
n/a
3
1
3
1
5
0
5
0
n/a
n/a
6
0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Output Current (mA)
I/O H
I/O L
(minimum) (minimum)
Clock
n/a
n/a
5.1
6.8
5.1
6.8
GMC0RxClk
5.1
6.8
GMC0RxClk
5.1
6.8
GMC0TxClk
5.1
6.8
GMC0TxClk
n/a
n/a
5.1
6.8
5.1
6.8
GMC1RxClk
5.1
6.8
GMC1RxClk
5.1
6.8
GMC1TxClk
5.1
6.8
GMC1TxClk
n/a
n/a
n/a
n/a
5.1
6.8
SMIIRefClk
5.1
6.8
SMIIRefClk
5.1
6.8
SMIIRefClk
5.1
6.8
SMIIRefClk
5.1
6.8
SMIIRefClk
27.7
12.8
27.7
12.8
27.7
12.8
27.7
12.8
27.7
12.8
27.7
12.8
15.3
10.2
n/a
n/a
n/a
n/a
19.1
8.7
n/a
n/a
n/a
n/a
n/a
n/a
19.1
8.7
n/a
n/a
19.1
8.7
n/a
n/a
n/a
n/a
n/a
n/a
19.1
8.7
n/a
n/a
n/a
n/a
Notes
async
async
async
async
async
AMCC Proprietary
77