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| 440EP Datasheet, PDF (7/84 Pages) Applied Micro Circuits Corporation – Power PC 440EP Embedded Processor | |||
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440EP â PPC440EP Embedded Processor
Revision 1.26 â April 25, 2007
Data Sheet
Table 1. System Memory Address Map (Sheet 2 of 2)
Function
Sub Function
Start Address
Reserved
0 EF50 0000
General Purpose Timer
0 EF60 0000
Reserved
0 EF60 0100
UART0
0 EF60 0300
Reserved
0 EF60 0308
UART1
0 EF60 0400
Reserved
0 EF60 0408
UART2
0 EF60 0500
Reserved
0 EF60 0508
UART3
0 EF60 0600
Reserved
0 EF60 0608
IIC0
0 EF60 0700
Reserved
0 EF60 0720
IIC1
0 EF60 0800
Internal Peripherals
Reserved
0 EF60 0820
SPI
0 EF60 0900
Reserved
0 EF60 0907
OPB Arbiter (OPB 0)
0 EF60 0A00
Reserved
0 EF60 0A40
GPIO0 Controller
0 EF60 0B00
Reserved
0 EF60 0B80
GPIO1 Controller
0 EF60 0C00
Reserved
0 EF60 0C80
Ethernet PHY ZMII
0 EF60 0D00
Reserved
0 EF60 0D10
Ethernet 0 Controller
0 EF60 0E00
Ethernet 1 Controller
0 EF60 0F00
USB 1.1 Host
0 EF60 1000
Reserved
0 EF60 1080
EBC
0 F000 0000
Boot space (EBC Bank 0 and PCI)
0 FFE0 0000
Notes:
1. DDR SDRAM can be located anywhere in the Local Memory area of the memory map.
2. EBC and PCI are relocatable, but this map reflects the suggested configuration.
End Address
0 EF5F FFFF
0 EF60 00FF
0 EF60 02FF
0 EF60 0307
0 EF60 03FF
0 EF60 0407
0 EF60 04FF
0 EF60 0507
0 EF60 05FF
0 EF60 0607
0 EF60 06FF
0 EF60 071F
0 EF60 07FF
0 EF60 081F
0 EF60 08FF
0 EF60 0906
0 EF60 09FF
0 EF60 0A3F
0 EF60 0AFF
0 EF60 0B7F
0 EF60 0BFF
0 EF60 0C7F
0 EF60 0CFF
0 EF60 0D0F
0 EF60 0DFF
0 EF60 0EFF
0 EF60 0FFF
0 EF60 107F
0 EFFF FFFF
0 FFDF FFFF
0 FFFF FFFF
Size
256B
8B
8B
8B
8B
32B
32B
6B
64B
128B
128B
16B
256B
256B
128B
254MB
2MB
AMCC Proprietary
7
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