PPC405EP Datasheet, PDF (46/50 Pages) Applied Micro Circuits Corporation – PowerPC 405EP Embedded Processor

PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
Table 14. I/O Specifications—Group 1 (Sheet 2 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.
3. For PCI, I_OH is specified at 0.9OV_DD and I_OL is specified at 0.1OV_DD. For all other interfaces, I_OH is specified at 2.4V and I_OL
is specified at 0.4V.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
Internal Peripheral Interface
IICSCL
na
na
IICSDA
na
na
UART0_CTS
na
na
UART0_RTS
na
na
UART0_Rx
na
na
UART0_Tx
na
na
UART1_Rx
na
na
UART1_Tx
na
na
Interrupts Interface
[IRQ0:6]
JTAG Interface
TCK
na
na
TDI
na
na
TDO
na
na
TMS
na
na
TRST
na
na
System Interface
GPIO00:31
na
na
Halt
na
na
SysErr
na
na
SysReset
na
na
TestEn
na
na
[RejectPkt0:1]
3
1
SysClk
na
na
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
Output Current (mA)
I_OH
(min)
I_OL
(min)
15.3
10.2
15.3
10.2
na
na
10.3
7.1
na
na
10.3
7.1
na
na
10.3
7.1
10.3
7.1
na
na
na
na
10.3
7.1
na
na
na
na
10.3
7.1
na
na
10.3
7.1
10.3
7.1
na
na
na
na
na
na
Clock
Notes
async
async
async
async
async
async
async
async
async
async
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AMCC