PPC405CR Datasheet, PDF (36/42 Pages) Applied Micro Circuits Corporation – PowerPC 405CR Embedded Processor

PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing value of na means “not applicable” and dc means
“don’t care.”
2. See “Test Conditions” on page 31 for output capacitive loading.
3. I/O H is specified at 2.4V; I/O L is specified at 0.4V
Table 13. I/O Specifications—All speeds
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
Internal Peripheral Interface
IICSCL
n/a
n/a
IICSDA
n/a
n/a
UART0_CTS
n/a
n/a
UART0_DCD
n/a
n/a
UART0_DSR
n/a
n/a
UART0_DTR
UART0_RI
n/a
n/a
UART0_RTS
UART0_Rx
n/a
n/a
UART0_Tx
UART1_RTS
[UART1_DTR]
UART1_DSR
[UART1_CTS]
n/a
n/a
UART1_Rx
n/a
n/a
UART1_Tx
UARTSerClk
n/a
n/a
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
DrvrInh1:2
dc
dc
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
Halt
dc
dc
RcvrInh
dc
dc
SysClk
SysErr
SysReset
TestEn
dc
dc
TmrClk
dc
dc
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10
1
n/a
n/a
n/a
n/a
Output Current (mA)
I/O H
(min)
I/O L
(min)
19
12
19
12
12
8
12
8
12
8
12
8
12
8
12
8
12
8
12
8
12
8
n/a
n/a
n/a
n/a
12
8
n/a
n/a
12
8
n/a
n/a
n/a
n/a
12
8
n/a
n/a
n/a
n/a
n/a
n/a
12
8
n/a
n/a
n/a
n/a
n/a
n/a
12
8
12
8
n/a
n/a
n/a
n/a
Clock Notes
async
async
async
async
async
async
async
async
async
async
36
AMCC