CS5320 Datasheet, PDF (33/160 Pages) Cirrus Logic – 24-Bit Variable Bandwidth A/D Converter Chipset

S5320 – PCI Match Maker: PCI Configuration Registers
Revision 5.03 – June 14, 2006
Data Sheet
PCI Status Register (PCISTS)
Register Name: ^{PCI Status}
Address Offset: ^06h-07h
Power-up value: ^0200h
Boot-load:
not used
Attribute:
Read Only Read/Write Clear
Size:
16 bits
This register contains PCI device status information.
This register is defined by the PCI specification and its
implementation is required of all PCI devices. Only
applicable bits are used by the S5320; those which are
not used are hardwired to 0. Status bits within this reg-
ister are designated as “write one clear,” meaning that
in order to clear a given bit, a 1 must be written. All R/
W/C bits written with a 0 are left unchanged. These
bits are identified in Figure 9 as (R/WC). Those which
are Read Only are shown as (RO).
Figure 9. PCI Status Register
15 14 13 12 11 10 9 8 7 6 54
XX0 0 0 01 0 1 0 0
0
Reserved = 00's
Reserved (RO)
66 Mhz Capable
UDF Supported
Fast Back-to-Back Capable
(RO)
Data Parity Reported (RO)
DEVSEL# Timing Status
00 = Fast
01 = Medium
10 = Slow
11 = Reserved
Signaled Target Abort (R/WC)
Received Target Abort (RO)
Received Master Abort (RO)
Signaled System Error (R/WC)
Detected Parity Error (R/WC)
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