PRSQ-80G Datasheet, PDF (3/4 Pages) Applied Micro Circuits Corporation – Switch Fabric

PRS Q-80G, PRS C48X, and PRS C192X
Switch Fabric
Product Brief
PB PRS Q-80G / v0.61 / 2-16-2006
AMCC Software, Evaluation Platforms, Reference
Designs, Development Tools, and Design Support for
Time-to-Market
To help Telecom Equipment Manufacturers to evaluate and prototype
complete solutions, shorten project cycles, mitigate development risks,
and optimize their development costs, PRS Q-80G evaluation
platforms, validated with evaluation boards from major NP/TM
vendors, are available from AMCC. They include an 80-Gbps switch
board (two devices) and a 320-Gbps switch board (eight devices) that
can be operated also in a 160-Gbps configuration.
Switch core reference designs incorporating the AMCC PowerPC
405EP control processor, software to operate the switch boards,
PC-based tool to initiate or monitor any operational or test function (for
example, traffic generation, digital eye, sense and operate of any bit,
loop back, and so on), board design services, and board
manufacturing capabilities complement the AMCC PRS offering.
PRS Q-80G Switch Core Device Features
The PRS Q-80G switch core device offers the following features:
• Non-blocking, single-stage, shared-memory switch
• Device aggregate throughput: 80 Gbps
• One-device switch: 40 Gbps of aggregate user bandwidth (16x16
ports at 2.5-Gbps/OC-48c speed, or 4x4 ports at 10-Gbps/OC-192c
speed)
• Two-device switch: 80 Gbps of aggregate user bandwidth (32x32
ports at 2.5-Gbps/OC-48c speed, or 8x8 ports at 10-Gbps/OC-192c
speed)
• 2.5-Gbps ports with speed-up factor of two (in conjunction with
PRS C48X fabric interface)
• 10-Gbps ports with speed-up factor of two (in conjunction with
PRS C192X fabric interface)
• 10-Gbps port operation in 4x 2.5-Gbps mode (in conjunction with
PRS C192X fabric interface)
• Embedded SerDes: 3.2-Gbps high-speed serial links, XAUI
compliant, with 8b/10b encoding for link synchronization and
supervision
• Multicast and broadcast without cell duplication in shared memory
(cell replication at sending)
• TDM traffic support
• Traffic priorities (CoS): up to four (configurable number)
• Output queue scheduling options: strict priority scheduling,
configurable credit table (weighted round-robin), exhaustive highest
priority first
• Redundant switch plane operations: hot standby or load sharing
mode, programmable scheduled switchover (cell lossless)
• Flow control based on a grant mechanism, subport flow control
• Programmable flow control thresholds for output queues, shared
memory, multicast/broadcast
• Fixed-length cells with configurable length (64, 72, or 80 bytes)
• Programmable cell header size: two, three, or five bytes,
independent of the switch configuration, containing destination
bitmap, packet priority, and switch redundancy support information,
all protected by a parity bit
• Local control processor interface (serial host interface)
• Reception (transmission) of control cells sent to (by) the local
processor on any input (output) port
• AMCC software for switch board control, PC-based development /
test tools
• Pin-to-pin and switch control software compatibility with PRS 64Gu
switch core
• Backward compatibility with PRS C48 or PRS C192 fabric
interfaces: SerDes operation at 2.5 Gbps (speed-up factor of 1.6)
Inter-operability in PRS Q-80G chassis: line cards with any of the
PRS C48, PRS C48X, PRS C192, and PRS C192X devices
PRS C48X and PRS C192X Fabric Interface Device
Features
• Port queuing manager (one per line card) between one or multiple
network processors and a PRS 80G or PRS Q-80G switch core
• PRS 80G or PRS Q-80G interface: embedded 3.2-Gbps SerDes,
with 8b/10b coding, and a speed-up factor of two, or eight between
the PRS Q-80G and PRS C48X
• PRS C48X: CSIX-L1 or PL3-based (POS-PHY Level 3 / OIF-SPI3-
01.0) 32-bit wide interface for 2.5-Gbps / OC-48 network processor
• PRS C192X: CSIX-L1 64-bit wide or 128-bit wide interface for 10-
Gbps / OC-192 network processor or, in subport mode, 4x CSIX-L1
or PL3-based (POS-PHY Level 3 / OIF-SPI3-01.0) 32-bit wide
interfaces for 2.5-Gbps / OC-48 network processors
• PRS C192X operation in subport (or quad PRS C48X) mode with
PRS 64Gu, PRS 80G, PRS Q-64G, and PRS Q-80G switch cores
• Dual-switch attachment for redundant switch plane operations
• Ingress virtual output queuing (VOQ), with up to 1024 unicast
queues and eight (PRS C48X) or 32 (PRS C192X) multicast
queues, preventing head-of-line blocking
• Up to four levels of traffic priority (CoS) and four programmable
ingress queue thresholds (ingress CSIX / PL3 flow control per
destination and priority)
• Shared ingress buffer and egress buffer capacities (configurable),
with sharing capability between planes
• Switch interface ingress cell scheduling: strict priority scheduling,
credit table (weighted round-robin), exhaustive highest priority first
• End-to-end cell payload protection, with optional cyclic redundancy
check insertion
• Internal loopback support for both the CSIX / PL3 interface and
switch interface
• Backward compatibility with PRS 64Gu switch core: SerDes
operation at 2.5 Gbps, with speed-up factor of 1.6
• Backward compatibility with PRS Q-64G switch core: SerDes
operation at 2.5 Gbps, with speed-up factor of 1.6 (PRS C192X) or
6.4 (PRS C48X)
• Inter-operability in PRS 64Gu and PRS Q-64G chassis: line cards
with any of the PRS C48 (PRS 64Gu chassis only), PRS C48X,
PRS C192, and PRS C192X devices
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