CS1201QFI22 Datasheet, PDF (2/2 Pages) Applied Micro Circuits Corporation – STS-12c/STS-3c POS/ATM SONET MAPPER

S1201 STS-12c/STS-3c POS/ATM SONET Mapper
Revision 3.4 - February 2002
PRODUCT BRIEF
Overview and Applications
SONET Processing
The S1201 performs standard STS-3c/STM-1 or
STS-12c/(STM-4/AU-4-4c) processing for both the transmit
and receive directions. ATM cells or PPP/LAPS packets are
mapped into the SONET/SDH SPE/VC, the POH, TOH/SOH
are inserted, and the resulting STS frame is transmitted in
byte wide format to the line-side interface. The reverse pro-
cess occurs when receiving data from the line-side. A TOH
interface provides direct add/drop capability for E1, E2, F1, &
both Section and Line DCC channels. The S1201 also
includes a clear channel mode that enables the direct trans-
mission of system payload from the system interface to the
line-side interface.
ATM Processing
When configured for ATM cell processing, the S1201’s trans-
mit ATM processor will perform all necessary cell encapsula-
tion including HEC generation, cell level scrambling (X⁴³+1),
and idle cell insertion to adapt the cell rate to the SPE. When
receiving data from the line side, it performs cell delineation,
Rx header control, descrambling, and receive cell rate adap-
tation. The S1201 also provides a full suite of status and con-
trol registers accessible via the microprocessor.
Packet/HDLC Processing
When configured for POS mode, the S1201’s transmit HDLC
processor provides the insertion of HDLC framed PPP/LAPS
packets into the STS SPE. It will perform packet framing,
inter-frame fill and Tx FIFO error recovery. In addition, it
optionally performs payload scrambling (X⁴³+1), performs
transparency processing as required by RFC 1662/ITU-T
COM7-D307 and will optionally generate a 16/32 bit CRC.
The receive HDLC processor provides for the extraction of
PPP/LAPS packets from HDLC frames, transparency
removal, de-scrambling (if enabled), FCS error checking and
optionally deletes the HDLC control and address fields. The
S1201 also provides a robust set of counters and status/con-
trol registers for performance monitoring via the microproces-
sor.
Line-side Interface
On the line-side, the S1201 supports an 8-bit parallel inter-
face which operates at 77.76/19.44 MHz when the device is
configured for STS-12c/STS-3c. The device is typically con-
nected to a parallel-to-serial converter, which is in turn con-
nected to an electrical-to-optical converter for interfacing to
the fiber optic interface. (See figure below.)
System Interface
The S1201 interface to the system link-layer device is via a
Utopia Level-2 compliant interface when operating in ATM
mode, and a POS-PHY^TM Level-2 compatible interface when
operating in Packet-Over-SONET mode. The interface oper-
ates at 25/50 MHz, as either 8 or 16 bits, in either Utopia or
POS-PHY^TM mode.
Microprocessor Interface
An 8-bit microprocessor interface is provided for device con-
trol and monitoring. The interface supports both Intel and
Motorola type microprocessors, and is capable of operating
in either an interrupt driven or polled-mode configurations.
Applications
ATM switches, Routers, IP switches, Virtual Networks.
Typical Application: S1201 in 622 Mb/s ATM or POS System
SONET
Line Side
Interface
Reference
Clock
Microprocessor
Control
9
8
Control Addr Data
Fiber Optic
Transceiver
SerTxD±
SerRxD±
HP HFCT5208
Sumitomo SDM7202
P/S & S/P
SONET XCVR
with
Clk Recovery
AMCC S3032
TX_SONETCLK
TX_DATA[7:0]
RX_LOS
RX_SONETCLK
RX_DATA[7:0]
AMCC
S1201
TX_CLK
TX_SYS_DAT[15:0]
Utopia Level-2
RX_CLK
RX_SYS_DAT[15:0]
or
POS-PHY^TM
System Interface
TOH Insertion
and Extraction
AMCC
200 Minuteman Park, Andover, MA 01810 Ph: [phone] Fax:[phone]