S3031B Datasheet, PDF (1/26 Pages) Applied Micro Circuits Corporation – E4/STM-1/OC-3 ATM TRANSCEIVER

DEVICE
SEPE4C/SIFTICMA-T1I/OONC-3 ATM TRANSCEIVER
E4/STM-1/OC-3 ATM TRANSCEIVER
FEATURES
• Complies with Bellcore and ITU-T
specifications
• On-chip high-frequency PLLs for clock
generation and clock recovery
• On-chip analog circuitry for transformer
driver and equalization
• Supports 139.264 Mbps (E4) and 155.52
Mbps (OC-3) transmission rates
• Supports 139.264 Mbps and 155.52 Mbps
Coded Mark Inversion (CMI) interfaces
• TTL Reference frequencies of 19.44 and
38.88 MHz (OC-3) or 17.408 and 34.816
MHz (E4)
• Interface to both PECL and TTL logic
• Lock detect on clock recovery function —
monitors run length and frequency
• Serial and 4 bit (nibble) system interfaces
• Low jitter PECL interface
• +5V operation
• 100 PQFP/TEP package
• Supports both electrical and optical interfaces
APPLICATIONS
• ATM over SONET/SDH
• OC-3/STM-1 or E4-based transmission
systems
• OC-3/STM-1 or E4 modules
• OC-3/STM-1 or E4 test equipment
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broadband cross-connects
• Fiber optic terminators
• Fiber optic test equipment
Figure 1a. Electrical Interface
®
S3031B
S3031B
GENERAL DESCRIPTION
The S3031B transceiver chip is a fully integrated CMI
encoding transmitter and CMI decoding receiver. The
chip derives high speed timing and data signals for
SONET/SDH or PDH-based equipment. The circuit is
implemented using AMCC’s proven Phase Locked Loop
(PLL) technology. Figures 1a and 1b show typical
network applications.
The S3031B has two independent VCOs which are
synchronized to the local NRZ transmitted data and the
received CMI data respectively. The chip can be used
with either a 19.44 MHz or a 38.88 MHz reference clock
when operated in the SONET/SDH OC-3 mode. In E4
mode the chip can be operated with a 17.408 MHz or a
34.816 MHz reference in support of existing system
clocking schemes. On-chip coded-mark-inversion (CMI)
encoding and decoding is provided for 139.264 Mbps
and 155.52 Mbps interfaces.
The low jitter PECL interface for the serial data inputs
and the PECL nibble clock interface guarantee com-
pliance with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3031B is packaged in a
0.65 mm pitch 100-pin PQFP/TEP.
The S3031B provides the major active components on-
chip for a coaxial cable interface, including analog
transformer driver circuitry and equalization interface
circuitry. Discrete controls permit separate selection of
CMI or NRZ operation and analog (coaxial copper) or
PECL (optical module) media interfaces. Both line
loopback and diagnostic local loopback operation are
supported.
E4/STM-1/OC-3
OVERHEAD
PROCESSOR
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps NRZ
OSC
Figure 1b. Optical Interface
17.408/19.44 MHz
S3031B
XCVR
139.264/155.52 Mbps CMI
COAX
XFMR
139.264/155.52 Mbps CMI
COAX
XFMR
E4/STM-1/OC-3
OVERHEAD
PROCESSOR
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps NRZ
OSC
17.408/19.44 MHz
S3031B
XCVR
139.264/155.52 Mbps
OTX
139.264/155.52 Mbps
ORX
August 19, 1999 / Revision D
1