S2042 Datasheet, PDF (1/20 Pages) Applied Micro Circuits Corporation – HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

PRELIMINARY
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S2042/S2043
S2042/S2043
FEATURES
• Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards
• S2042 transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
reference
• S2043 receiver PLL configured for clock and
data recovery
• 1062, 531 and 266 Mb/s operation
• 10- or 20-bit parallel TTL compatible interface
• 1 watt typical power dissipation for chipset
• +3.3/+5V power supply
• Low-jitter serial PECL compatible interface
• Lock detect
• Local loopback
• 10mm x 10mm 52 PQFP package
• Fibre Channel framing performed by receiver
• Continuous downstream clocking from receiver
• TTL compatible outputs possible with +5V I/O
power supply
APPLICATIONS
High-speed data communications
• Supercomputer/Mainframe
• Workstation
• Switched networks
• Proprietary extended backplanes
• Mass storage devices/RAID drives
GENERAL DESCRIPTION
The S2042 and S2043 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chipset is select-
able to 1062, 531 or 266 Mbit/s data rates with
associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2042 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2043
on-chip PLL synchronizes directly to incoming digital
signals to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Lo-
cal loopback allows for system diagnostics. The TTL
I/O section can operate from either a +3.3V or a +5V
power supply. With a 3.3V power supply the chipset
dissipates only 1W typically.
Figure 1 shows a typical network configuration incor-
porating the chipset. The chipset is compatible with
AMCC’s S2036 Open Fiber Control (OFC) device.
Figure 1. System Block Diagram
S2036
Open
Fiber
Control
(OFC)
Fibre
Channel
Controller
S2042
TX
S2043
RX
Optical
TX
Optical
RX
Optical
RX
Optical
TX
S2043
RX
S2042
TX
Fibre
Channel
Controller
S2036
Open
Fiber
Control
(OFC)
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • [phone]
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