CS4811 Datasheet, PDF (1/5 Pages) Cirrus Logic – Fixed Function Multi-Effects Audio Processor

TIGRIS
OC-48 Multi Protocol Termination for 2047 Channels
FINAL ProFdIuNctABLriefProduct Brief
Part NuPmabrteNr _{uSm48b1e1r, SR4e8v1.12,.4ReJvu.ly2.240J0u6ly 2006}
TIGRIS is a high density data-termination device supporting 2047 channels operating at an aggregate rate of 2.488Gbps. The
device aggregates and terminates both ATM cells and HDLC frames, enabling ATM services such as Cell Relay, IMA, AAL2/5, and
frame based services, such as PPP, Frame Relay, and Multi-link PPP and Multi-link Frame Relay. The 2047 individually assignable
channels can be configured for Frame Relay, HDLC, PPP, and or ATM services for DS0, NxDS0, DS1/E1, DS3/E3, STS-1c, STS-3c
and STS-12c rates.
TIGRIS supports up to 48 channels of subrate DS3 services interoperating with major CSU/DSU vendors protocols and can be com-
bined with AMCC’s nP3700 to provide AAL2/5, IMA, and Multilink services for all 2047 channels.
Data Sseerrvviicceess aanndd pPeerrffoorrmmaannccee mMoonniittoorriinngg
• Store and forward architecture with extensive buffering using
external DDR SDRAM.
• 2047 bi-directional ATM/HDLC channels that can be
assigned to tributaries from STS-12 to DS0.
• Bit Ssyynncchhrroonnoouuss HHDDLLCC ssuuppppoorrtt all channels (DS3 and lower
rate).
• Byte synchronous HDLC support for all channels (STS-1 and
higher rate).
• Direct Map ATM support.
• G.832 E3 ATM support.
• Support for up to 48 DS3 PLCP ATM mapped channels.
• Support for up to 48 Ssuubb--rRataeteDDSS33chcahnanenlesl.s.
FTI-2 LlinineeinInteterrfafaccee
• Four independent STS-12 capable interfaces selectable from
four serial 622 MHz LVDS Flexible Tributary interfaces (FTI-
2) or one Parallel FTI 8-bit x 78MHz Interface. Parallel
Interface is compatible with standard Telecom Bus interfaces.
• An Eexpaannssiioonn mode allows multiple TIGRIS devices to share
a single FTI interface (allows up to 8K channels).
• Glueless interface to up to four AMCC Evros framers.
System Interface
• SPI-3 32bit @ 104MHz for cells/packets and error status.
• The SPI-3 supports four interleaved channels (four logical
PHY ports).
• Pre-pended packet tag for channel ID, length, error status,
TX queue priority, and TX per packet loopback.
Device Specifications
• 899 PBGA (31x31mm with 1mm ball pitch) package with
• 1G.r2eVenc/oRreo,H2S.5cVomI/Opliant ^option
•• E1.s2tVimcaotered, 32W.5VpoI/wOer consumption
• 6.0W maximum power consumption
Figure 1: Block Diagram
SERIAL
ATI
INTERFACES
EXTERNAL
SDRAM
(RX Frame storage)
EXTERNAL
SDRAM
(TX Frame storage)
PARALLEL 8 BIT @77Mhz
INTERFACE _{LTX_DATA[7:0]]}
LTX_CONTROL_SIGNALS
LRX_DATA[7:0]]
LRX_CONTROL_SIGNALS
4 x 622Mhz LVDS
SERIAL INTERFACES
SCLK
LTX_DATA622[3:0]
LTX_CLK622[3:0]
LTX_CONTROL622[3:0]
LRX_DATA622[3:0]
LRX_CLK622[3:0]
LRX_CONTROL622[3:0]
12
24
TRANSMIT
4X FTI
FRAMER
ATI SERIAL CLK and
DATA I/F
SUBRATE
DS3
/ DS3
PLCP
FRAMER
HDLC / ATM
Processor
EXTERNAL MEMORY I/F
MEMORY
MANAGER
TRANSMIT
FIFO
QUEUE MANAGER
RECEIVE
4X FTI
FRAMER
PMON
JTAG PORT
MICROPROCESSOR I/F
RECEIVE
FIFO
TDAT[0:31]
TSX
TSOP
TPRTY
TMOD[1:0]
TERR
TEOP
TENB
TFCLK
RSA[3:0]
STPA
PTPA
DTPA[3:0]
TADR[1:0]
RFCLK
RSX
RSOP
RPRTY
RMOD[1:0]
RERR
REOP
RENB
RVAL
RDAT[0:31]
FINAL Information - The information contained in this document is
about a product that has been fully tested, characterized, and is produc-
tion released. All features described herein are supported. Contact
AMCC for updates to this document and the latest product status.
Empowering Intelligent Optical Networks