CS19208CBI Datasheet, PDF (1/4 Pages) Applied Micro Circuits Corporation – OC-192/48/12/3 DW/FEC/PM and ASYNC Mapper Device

Niagara
OC-192/48/12/3 DW/FEC/PM and ASYNC Mapper Device
Product Brief
Part Number S19208CBI, Revision 1.4, Jan 2003
Features
G.709 ODU - 2 Synchronous and Asynchronous mapping
• 1 x OC – 192/STM-64 mapping (239,237)
• Direct map (239,238) into ODU – 2
G.709 ODU - 1 Synchronous and Asynchronous mapping
• 1 x OC – 48/STM-16 mapping (239,237)
• Direct map (239,238) into ODU – 1
G.709 Overhead processing
• Bi-directional add-drop ODU – 1, ODU – 2
• Bi-direction G.709 Overhead Processing
• Dedicated GCC ports
Ingress and Egress SONET/SDH Performance Monitoring/
Injection
• 1 x OC-192/48/12/3 TOH add-drop and processing
• 8B/10B Monitoring
• 10GE Monitoring
• SONET/SDH section and line termination
• TOH add-drop port
• LOS, OOF, LOF detection
• B1, B2 monitoring with programmable Signal Degrade and Signal
Fail thresholds
• J0 Monitoring, SDH and SONET modes
• Support for Protection Switching
• K1, K2 monitoring for APS changes, line AIS and line RDI
• Automatic, interrupt-driven, or manual AIS insertion
• Frame boundary output
Industry Standard RS(255,239) Forward Error Correction with 6.2
dB Coding Gain (at 10^-15 CER)
• G.709 Compliant Frame Structure
• Compatible with AMCC S19203 (Hudson)
Enhanced Gain Forward Error Correction with G.709 ODU
• 10.71, 10.66, and 11.1 Gbps enhanced FEC with >8dB coding gain
• G.709 overhead processing and nominal rate expansion
• Comprehensive channel statistics gathering
• Corrected bits, bytes
• Corrected zeros, ones (with outputs)
• Uncorrectable sub-frame count
Broad Interface Compatibility
• 16 bit, 622 Mbps LVDS interface (OIF MSA compliant) 10 Gbps
interface
• Compatible with AMCC Hudson, Ganges, S3091/92, S3097/98,
S19211, S3193/S3094, and S3474
Client and Line side loop-back
• Client-side loopback on single 10 Gbps interface
• Line loopback on 10 Gbps interface
Support For System Test and Diagnostics
• Can synthesize SONET frame
• Error injection capability for verification of remote error reporting
• Test set compliant pseudo-random sequence generation/analysis
General Purpose Processor Interface
• Glueless interface to MPC860, 25 MHz to 52 MHz
• Dual Mode Interface also supports Intel processors
• Interrupt Driven or Polled mode operation
Additional Protocol Support
• FEC Frame Synchronous scrambling
• Programmable sequence detection
Low Power .18 u CMOS Technology
• 1.8 Volt core operation
• 2.5 Volt I/O
OTN Network/Line
Interface
Figure 1: Block Diagram
Ingress/EgressOD
U-2 OH Add/Drop
IngressEgress
SONET/SDH
TOH Add/Drop
Client or OTN
Interface
Pattern
& Err
Analysis
EFEC
Decoder
BYPASS
BYPASS
PN gen
Err Ins
EFEC
Encoder
SFI-4 (10 GBPS)
Register
Map
Interrupt
Control
8 or 16 uP I/F
OC-192
PM
10GE
PM
BYPASS
BYPASS
OC-192
PM
10GE
PM
R-S
FEC
Encoder
PN gen
Err Ins
BYPASS
BYPASS
R-S
FEC
Decoder
Pattern
& Err
Analysis
SFI-4 (10 GBPS)
Final/Production ReleaseInformation - The information contained in this docu-
ment is about a product in its fully tested and characterized phase. All features
described herein are supported. Contact AMCC for updates to this document and
the latest product status.
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