CS19205CBI Datasheet, PDF (1/3 Pages) Applied Micro Circuits Corporation – 10 Gigabit Ethernet MAC and PHY/OC-192c POS Framer/Mapper

KHATANGA
10 Gigabit Ethernet MAC and PHY/OC-192c POS Framer/Mapper
Features
• Single STS-192c/STM-64 framer/mapper device to support 10
Gigabit Ethernet (10GbE) serial WAN, serial LAN and STS-192c/
AU-4-64c POS applications.
• Supports full duplex mapping of Ethernet frames into a single
SONET/SDH STS-192c/AU-4-64c (WIS functionality) in compliance
with IEEE P802.3ae / D2.0 proposed baseline specification for
10GbE over the WAN.
• SONET/SDH section/line/path processing compliant with Telcordia
GR-253, ANSI T1.105 and T1.416, and ITU G.751, G.783 and
G.804. Provides a subset of the full SONET/SDH processing which
implements the P802.3ae / D2.0 defined 10GbE WAN Interface
Sublayer (WIS).
• Performs 10GbE MAC processing, compliant with IEEE P802.3ae /
D2.0.
• Performs 64B/66B encoding in the TX direction and 64B/66B
decoding in the RX direction when operating in 10GbE mode.
• A WIS bypass mode is provided, to support 10GbE serial LAN
applications.
• Supports external MAC implementations.
• Alternatively, supports full-duplex mapping of packets in a single
SONET/SDH STS-192c/AU-4-64c per IETF 2615 (POS).
• SONET/SDH processing includes termination and generation of
section, line, & path layers, with transport/section and path over-
head interfaces in both transmit and receive directions.
Product Brief
Part Number S19205CBI, Revision 1.4, October 2002
• POS processing includes HDLC framing, payload scrambling (x⁴³ +
1) and transparency processing.
• 10GbE MAC transmit processing includes frame assembly, pad
insertion, and CRC generation.
• 10GbE MAC receive processing includes Ethernet framing, CRC
checking, and frame size monitoring.
• Supports 802.3x PAUSE flow control.
• Provides counters to support implementation of RMON, 802.3
MIBs.
• Provides a 622.08 MHz 16-bit bus interface on the line side in both
the TX and RX directions (SFI-4/XSBI compliant).
• Provides a 644 MHz 16-bit LVDS interface on the line side in both
TX and RX directions for LAN PHY applications (XSBI).
• Provides a 64-bit, 200 MHz FlexBus-4^TM system interface (SPI-4
Phase 1 compliant).
• Direct Map Mode for mapping of any traffic type in SONET/SDH
STS-192c/AU-4-64c payloads
• 16-bit synchronous microprocessor interface for configuration, con-
trol, and status monitoring.
• Provides a 622.08 MHz 16-bit line bus to support Automatic Protec-
tion Switching (APS) configurations.
• Packaged in a 624-pin CBGA.
• Implemented in .18 micron CMOS, 1.8V and 2.5V technology.
Figure 1: Block Diagram
TX_CLK_OUT
TX_DATA_OUT[15:0]
RX_DATA_IN[15:0]
RX_CLK_IN
LOC
DET
MUX TOHINSERT
FRG_FE_RN_TX
MUX
LBK
SEL
FRMR
TOH
MON.
TOH EXTRACT
FRM
SPE
GEN
POH
MON
PTR
INT
MICROPROCESSOR I/F
64B66B
EEnnccooddeerr
64B66B
Decoder
JTAG
10G
MAC
HDLC
Proc
HDLC
Proc
10G
MAC
SYSTEM
INTRFC
FIFO
Control
STX_DATA_IN[63:0]
SYSTEM
INTRFC
FIFO
SRX_DATA_OUT[63:0]
Control
FInal Production Release Information - The information contained in this docu-
ment is about a product in its fully tested and characterized stage. All features
described herein are supported. Contact AMCC for updates to this document and
the latest product status.
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