CS19203CBI20 Datasheet, PDF (1/3 Pages) Applied Micro Circuits Corporation – Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device

HUDSON 2.0
Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device
Product Brief
Part Number S19203CBI20, Revision 1.3, May 2003
The Hudson is a fully integrated, Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, and Forward Error Correction (FEC)
device supporting the Digital Wrapper transmission standards for OTU1, OTU2, ODU1, ODU2, OPU1, and OPU2 as specified in G.709. The
Hudson implements Performance Monitoring and overhead processing functions on the Digital Wrapper overhead bytes. In addition, the
device contains SONET/SDH Performance Monitoring to verify the validity of the SONET/SDH OC-192 client data. The device can operate
from a low rate of 6.25 MHz to a high rate of 693.483 MHz. Data entering and leaving the chip can be optionally deframed and framed,
descrambled and scrambled, and decoded and encoded with forward error correction information.
• Core logic runs on a 1.8 V power supply to reduce power con-
sumption and LVCMOS I/O are 3.3 V compatible.
• Two independent 16-bit parallel LVDS input and output ports at
up to 693.483 MHz (11.096 Gbps).
• Datapath options: Configurable as two completely independent
data stream for full duplex operation. Configurable as a single
data stream for regenerator operation with dual redundant I/O for
optional protection switching. Either input port can be directly
connected to either output port for loopback testing or bypass
operation.
• Supports SONET OC-192 Performance Monitoring at the input of
the encoder side and at the output of the decoder side.
• Supports G.709 “Interfaces for the optical transport network
(OTN)” standard including specified frame structure, all overhead
monitoring and processing, Maintenance signals, synchronous
and asynchronous mapping and demapping.
• ON/OFF control of Reed-Solomon (255,239) FEC Encoding/
Decoding and error correction.
• Support for System test and diagnostics: internal BER generator,
PRBS pattern generator and pattern analyzer for bit error rate
testing capability.
• Four programmable integer clock dividers to simplify clock gener-
ation.
• Support for signal aggregation to higher rates via chip synchroni-
zation feature.
• General Purpose Processor Interface: Gluess interface to
MPC860, 25 MHz to 50 MHz bus speed. Also compatible with
Intel microprocessor bus via Busmode selector.
• Low power: 0.18 micron CMOS technology.
Applications
• 10 Gigabit Digital Wrapper Performance Monitor and Framer
• Protocol Independent DWDM Metropolitan Area Networks
• Optical Cross-connects
• OC-192 Port interface
• Fiber optic terminators, repeaters, and test equipment
Hudson 2.0
D ECO DEIN[15:0]
D EC R XC LK
DEC
1 :8
Demux
D EC R XC LK _D IV
Clock
Divider
RX_OH_CLK
RX _O H_D ATA[7:0]
DROPFP
DROPSFP
INPUT_PORT _SW AP
0
1
E N C _D R PC LK
ENC _DRP [7:0]
ENC_DRP_FP
ENC_DRP_SFP
Figure 1: Block Diagram
D EC _IN_SEL[1:0]
00
DEC OH
F ram er
0 0,10
10
01
Decode (DEC ) S ide
01
FEC
11
D ecoder
00
R a te
M a tch
F IF O
DEC OH
M on/Drop
P a tte rn
Analyzer
DEC OH
Ins &
Scrambler
DU P_OUT _SEL[1:0]
DEC
SONET
PM
01, 11
00
10
O UTPUT_PO RT_SW AP
0
DUPO
1
UT 1:8
Mux
DUP LEXO UT[15:0]
DUPTXCLK_OUT
Clock
Divider
D U PT XC LK _D IV
Sync
B uffer
DE C_IN SCLK
D EC _IN S_F P
D EC _IN S _S F P
DEC IN S[7:0]
DE C_IN S_EN
D U P L E X IN [1 5:0 ]
DUPRXCLK
D U PIN
1 :8
Demux
1
0
IN PUT_PO RT_SW AP
D U PR X C LK_D IV
C lock
D ivider
DUP OH
F ra m e r
ENC
SONET
PM
OCH
D e s c ra m
& S C/O H
M on/D rop
P attern
G enerator
1
00
0
10
0
01
1
EN C_IN_SEL
PAT _GEN_ON
Rate
M atch
FIFO
ENC OH
F ra m e
Gen &
FEC
Encoder
ENC OH
Add
00, 01
10
1
0
O UTPU T_POR T_SW AP
ENC
8 :1
Mux
EN CDA TAO U T[15:0]
ENCTXCLK
TX_OH_CLK
INSFP
T X _ OIHN_SDSAFTPA [7 :0]
TX_O H _IN S
Encode (EN C) Side
ENC_O UT_SEL[1:0]
Clock
Divider
ENC TXCLK _DIV
FINAL/PRODUCTION RELEASE Information - The information contained in this
document is about a product in its fully tested and characterized phase. All fea-
tures described herein are supported. Contact AMCC for updates to this docu-
ment and the latest product status.
Empowering Intelligent Optical Networks