EP5368QI Datasheet, PDF (9/14 Pages) Enpirion, Inc. – 600mA Synchronous Buck Regulator With Integrated Inductor

When operating in VID mode, the maximum
total capacitance on the output, including the
output filter capacitor and bulk and decoupling
capacitance, at the load, is given as:
C_{OUT_TOTAL_MAX} = C_{OUT_Filter} + C_{OUT_BULK} = 700uF
When the EP5368QI output voltage is
programmed using and external resistor divider
the maximum total capacitance on the output is
given as:
C_{OUT_TOTAL_MAX} = 1.251x10^-3/V_OUT Farads
The above number and formula assume a no
load condition at startup.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling V_OUT low. This condition is maintained
for a period of 1mS and then a normal soft start
is initiated. If the over current condition still
persists, this cycle will repeat in a “hiccup”
mode.
Application Information
Output Voltage Select
To provide the highest degree of flexibility in
choosing output voltage, the EP5368QI uses a
3 pin VID, or Voltage ID, output voltage select
arrangement. This allows the designer to
choose one of seven preset voltages, or to use
an external voltage divider. Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output
voltage
selected.
EP5368QI
Under Voltage Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold,
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the converter
and cause it to shut down. A logic high will
enable the converter into normal operation. In
shutdown mode, the device quiescent current
will be less than 1 uA.
NOTE: This pin must not be left floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C, the
device will go through the normal startup
process.
Table 1 shows the various VS0-VS2 pin logic
states and the associated output voltage
levels. A logic “1” indicates a connection to
VIN or to a “high” logic voltage level. A logic
“0” indicates a connection to ground or to a
“low” logic voltage level. These pins can be
either hardwired to VIN or GND or alternatively
can be driven by standard logic levels. Logic
low is defined as VLOW ≤ 0.4V. Logic high is
defined as VHIGH ≥ 1.4V. Any level between
these two values is indeterminate. These pins
must not be left floating.
03260
9
October 11, 2013
www.altera.com/enpirion
Rev H