EP1K30FC256-2 Datasheet, PDF (81/86 Pages) Altera Corporation – Programmable Logic Device Family

ACEX 1K Programmable Logic Device Family Data Sheet
Table 57. EP1K100 External Bidirectional Timing Parameters Notes (1), (2)
Symbol
Speed Grade
-1
-2
-3
Min
Max
Min
Max
Min
Max
t_INSUBIDIR (3)
1.7
2.5
3.3
t_INHBIDIR (3)
0.0
0.0
0.0
t_INSUBIDIR (4)
2.0
2.8
–
t_INHBIDIR (4)
0.0
0.0
–
t_OUTCOBIDIR (3)
2.0
5.2
2.0
6.9
2.0
9.1
t_XZBIDIR (3)
5.6
7.5
10.1
t_ZXBIDIR (3)
5.6
7.5
10.1
t_OUTCOBIDIR (4)
0.5
3.0
0.5
4.6
–
–
t_XZBIDIR (4)
4.6
6.5
–
t_ZXBIDIR (4)
4.6
6.5
–
Notes to tables:
(1) All timing parameters are described in Tables 22 through 29 in this data sheet.
(2) These parameters are specified by characterization.
(3) This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(4) This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power
Consumption
The supply power (P) for ACEX 1K devices can be calculated with the
following equation:
P = P_INT + P_IO = (I_CCSTANDBY + I_CCACTIVE) × V_CC + P_IO
The I_CCACTIVE value depends on the switching frequency and the
application logic. This value is calculated based on the amount of current
that each LE typically consumes. The P_IO value, which depends on the
device output load characteristics and switching frequency, can be
calculated using the guidelines given in Application Note 74 (Evaluating
Power for Altera Devices).
1
Compared to the rest of the device, the embedded array
consumes a negligible amount of power. Therefore, the
embedded array can be ignored when calculating supply
current.
13
Altera Corporation
81