ES1030QI Datasheet, PDF (6/14 Pages) Altera Corporation – Power Rail Sequencer

Typical Application Circuits
ES1030QI
Figure 3: Stand Alone Operation
Notes to Figure 3:
1. Unused PG pins may be floated or tied to VDD.
2. ACNTL controls delays based on voltage ratio relative to REF_O: full scale delay (ACTRL at REF_O) is
8.04ms; minimum delay (ACTRL at GND) is 33us.
3. For single device, connect NEXT_O to NEXT_IN.
4. Tie all nFAULT_x pins of all chained devices together. When fault is detected in any device, the device
pulls the nFAULT line low, triggering sequential power down starting with the end device. This is
released by EN low until FAULT is cleared.
5. ALL_PG is a push-pull output for logical AND of all PG_x signals.
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