EPF10K30RC208-3 Datasheet, PDF (59/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
Dedicated
Clock
OE Register
PRN
DQ
CLRN
Output Register
PRN
DQ
t_XZBIDIR
t_ZXBIDIR
t_OUTCOBIDIR
Bidirectional
Pin
CLRN
t_INSUBIDIR
t_INHBIDIR
Input Register
PRN
DQ
CLRN
Tables 32 through 36 describe the FLEX 10K device internal timing
parameters. These internal timing parameters are expressed as worst-case
values. Using hand calculations, these parameters can be used to estimate
design performance. However, before committing designs to silicon,
actual worst-case performance should be modeled using timing
simulation and analysis. Tables 37 through 38 describe FLEX 10K external
timing parameters.
Table 32. LE Timing Microparameters (Part 1 of 2) Note (1)
Symbol
t_LUT
t_CLUT
t_RLUT
t_PACKED
t_EN
t_CICO
t_CGEN
t_CGENR
t_CASC
t_C
t_CO
t_COMB
Parameter
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
Cascade-in to cascade-out delay
LE register control signal delay
LE register clock-to-output delay
Combinatorial delay
Conditions
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