EP1C12F256C8N Datasheet, PDF (58/106 Pages) Altera Corporation – Section I. Cyclone FPGA Family Data Sheet

Cyclone Device Handbook, Volume 1
Advanced I/O Standard Support
Cyclone device IOEs support the following I/O standards:
■ 3.3-V LVTTL/LVCMOS
■ 2.5-V LVTTL/LVCMOS
■ 1.8-V LVTTL/LVCMOS
■ 1.5-V LVCMOS
■ 3.3-V PCI
■ LVDS
■ RSDS
■ SSTL-2 class I and II
■ SSTL-3 class I and II
■ Differential SSTL-2 class II (on output clocks only)
Table 2–12 describes the I/O standards supported by Cyclone devices.
Table 2–12. Cyclone I/O Standards
I/O Standard
Type
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI (1)
LVDS (2)
RSDS (2)
SSTL-2 class I and II
SSTL-3 class I and II
Differential SSTL-2 (3)
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
Differential
Voltage-referenced
Voltage-referenced
Differential
Input Reference Output Supply
Voltage (V_REF) (V) Voltage (V_CCIO) (V)
Board
Termination
Voltage (V_TT) (V)
N/A
3.3
N/A
N/A
2.5
N/A
N/A
1.8
N/A
N/A
1.5
N/A
N/A
3.3
N/A
N/A
2.5
N/A
N/A
2.5
N/A
1.25
2.5
1.25
1.5
3.3
1.5
1.25
2.5
1.25
Notes to Table 2–12:
(1) There is no megafunction support for EP1C3 devices for the PCI compiler. However, EP1C3 devices support PCI
by using the LVTTL 16-mA I/O standard and drive strength assignments in the Quartus II software. The device
requires an external diode for PCI compliance.
(2) EP1C3 devices in the 100-pin TQFP package do not support the LVDS and RSDS I/O standards.
(3) This I/O standard is only available on output clock pins (PLL_OUT pins). EP1C3 devices in the 100-pin package
do not support this I/O standard as it does not have PLL_OUT pins.
Cyclone devices contain four I/O banks, as shown in Figure 2–35. I/O
banks 1 and 3 support all the I/O standards listed in Table 2–12. I/O
banks 2 and 4 support all the I/O standards listed in Table 2–12 except the
3.3-V PCI standard. I/O banks 2 and 4 contain dual-purpose DQS, DQ,
2–52
Preliminary
Altera Corporation
May 2008