EP1K100FC256-2N Datasheet, PDF (53/86 Pages) Altera Corporation – Programmable Logic Device Family

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
Dedicated
Clock
OE Register
PRN
DQ
t_XZBIDIR
t_ZXBIDIR
CLRN
Output Register
PRN
DQ
t_OUTCOBIDIR
Bidirectional
Pin
CLRN
t_INSUBIDIR
t_INHBIDIR
Input Register
PRN
DQ
CLRN
Tables 29 and 30 show the asynchronous and synchronous timing
waveforms, respectively, for the EAB macroparameters in Table 24.
Figure 29. EAB Asynchronous Timing Waveforms
EAB Asynchronous Read
WE
Address
Data-Out
a0
a1
t_EABAA
d0
d1
a2
t_EABRCCOMB
d2
EAB Asynchronous Write
WE
Data-In
Address ^a0
din0
t_EABWASU
Data-Out
t_EABWP
t_EABWDSU
t_EABWCCOMB
a1
din0
din1
t_EABWDH
t_EABWAH
t_EABDD
din1
a3
d3
a2
dout2
13
Altera Corporation
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