EPM7128AETC100-10 Datasheet, PDF (52/64 Pages) Altera Corporation – High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX

MAX 7000A Programmable Logic Device Data Sheet
Table 29. EPM7256A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-12
Min Max Min Max Min Max Min Max
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_CNT
f_CNT
t_ACNT
f_ACNT
Input to non-registered C1 = 35 pF
6.0
7.5
output
(2)
I/O input to non-
C1 = 35 pF
6.0
7.5
registered output
(2)
Global clock setup time (2)
3.7
4.6
Global clock hold time (2)
0.0
0.0
Global clock setup time
of fast input
2.5
3.0
Global clock hold time of
fast input
0.0
0.0
Global clock to output
delay
C1 = 35 pF 1.0 3.3 1.0 4.2
Global clock high time
3.0
3.0
Global clock low time
3.0
3.0
Array clock setup time (2)
0.8
1.0
Array clock hold time (2)
1.9
2.7
Array clock to output
delay
C1 = 35 pF 1.0 6.2 1.0 7.8
(2)
Array clock high time
3.0
3.0
Array clock low time
3.0
3.0
Minimum pulse width for (3)
3.0
3.0
clear and preset
Minimum global clock (2)
period
6.4
8.0
Maximum internal global (2), (4)
clock frequency
156.3
125.0
Minimum array clock (2)
period
6.4
8.0
Maximum internal array (2), (4)
clock frequency
156.3
125.0
10.0
12.0 ns
10.0
12.0 ns
6.2
7.4
ns
0.0
0.0
ns
3.0
3.0
ns
0.0
0.0
ns
1.0 5.5 1.0 6.6 ns
4.0
4.0
ns
4.0
4.0
ns
1.4
1.6
ns
4.0
5.1
ns
1.0 10.3 1.0 12.4 ns
4.0
4.0
ns
4.0
4.0
ns
4.0
4.0
ns
10.7
12.8 ns
93.5
78.1
MHz
10.7
12.8 ns
93.5
78.1
MHz
52
Altera Corporation