EPM7064SLC44-10N Datasheet, PDF (51/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Tables 37 and 38 show the EPM7256S AC operating conditions.
Table 37. EPM7256S External Timing Parameters
Symbol
Parameter
Conditions
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_ODH
t_CNT
f_CNT
t_ACNT
f_ACNT
f_MAX
Input to non-registered output C1 = 35 pF
I/O input to non-registered
output
C1 = 35 pF
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay C1 = 35 pF
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
C1 = 35 pF
Array clock high time
Array clock low time
Minimum pulse width for clear (2)
and preset
Output data hold time after
clock
C1 = 35 pF (3)
Minimum global clock period
Maximum internal global clock (4)
frequency
Minimum array clock period
Maximum internal array clock (4)
frequency
Maximum clock frequency
(5)
Note (1)
Speed Grade
Unit
-7
-10
-15
Min Max Min Max Min Max
7.5
10.0
15.0 ns
7.5
10.0
15.0 ns
3.9
7.0
11.0
ns
0.0
0.0
0.0
ns
3.0
3.0
3.0
ns
0.0
0.5
0.0
ns
4.7
5.0
8.0
ns
3.0
4.0
5.0
ns
3.0
4.0
5.0
ns
0.8
2.0
4.0
ns
1.9
3.0
4.0
ns
7.8
10.0
15.0 ns
3.0
4.0
6.0
ns
3.0
4.0
6.0
ns
3.0
4.0
6.0
ns
1.0
1.0
1.0
ns
7.8
10.0
13.0 ns
128.2
100.0
76.9
MHz
7.8
10.0
13.0 ns
128.2
100.0
76.9
MHz
166.7
125.0
100.0
MHz
Altera Corporation
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