EPM7128SLC84-15 Datasheet, PDF (5/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide range of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP packages. See Table 5.
Table 5. MAX 7000 Maximum User I/O Pins Note (1)
Device
44- 44- 44- 68- 84- 100- 100- 160-
Pin Pin Pin Pin Pin Pin Pin Pin
PLCC PQFP TQFP PLCC PLCC PQFP TQFP PQFP
EPM7032 36 36 36
EPM7032S 36
36
EPM7064 36
36 52 68 68
EPM7064S 36
36
68
68
EPM7096
52 64 76
EPM7128E
68 84
100
EPM7128S
68 84 84 (2) 100
EPM7160E
64 84
104
EPM7160S
64
84 (2) 104
EPM7192E
124
EPM7192S
124
EPM7256E
132 (2)
EPM7256S
160-
Pin
PGA
124
192- 208- 208-
Pin Pin Pin
PGA PQFP RQFP
164
164
164 (2) 164
Notes:
(1) When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins
become JTAG pins.
(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see
the Operating Requirements for Altera Devices Data Sheet.
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independent combinatorial and sequential logic functions. The
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.
Altera Corporation
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