EPC1PI8N Datasheet, PDF(5/26 Page) Altera Corporation – Configuration Devices for SRAM-Based LUT Devices

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EPC1PI8N Datasheet, PDF (5/26 Pages) Altera Corporation – Configuration Devices for SRAM-Based LUT Devices

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Functional Description

Page 5

Table 2. Supported Configuration Devices (Part 4 of 4)

Device Family

Device

Data Size (Bits) EPC1064 or

(1)

EPC1064V

EP2S15

5,000,000

EP2S30

10,100,000

Stratix II

EP2S60

EP2S90

17,100,000

27,500,000

EP2S130

39,600,000

EP2S180

52,400,000

Notes to Table 2:

(1) Raw Binary File (.rbf) were used to determine these sizes.

(2) This number is calculated with the Cyclone series compression feature enabled.

(3) EP1S10 ES devices requires four EPC2 devices.

EPC1213 EPC1441

Figure 1 shows the configuration device block diagram.

Figure 1. Configuration Device Block Diagram

EPC1

FPGA (except FLEX 8000) Configuration Using an EPC2, EPC1, or EPC1441

nCS

(2) OE

Oscillator

Control

Error

Detection

Circuitry

CLK

ENA

nRESET

Address

Counter

Address

Decode

Logic

EPROM

Array

DATA

Shift

DCLK

nCASC (1)

DATA

FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V

DCLK

CLK

ENA

nRESET

Address

Counter

Address

Decode

Logic

nCS

nCASC (1)

EPROM

Array

DATA

Shift

DATA

Notes to Figure 1:

(1) The EPC1441 devices do not support data cascading. The EPC1, EPC2, and EPC1213 devices support data cascading.

(2) The OE pin is a bidirectional open-drain pin.

EPC2

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

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