EPM7160STI100-10 Datasheet, PDF (49/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Table 35. EPM7192S External Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
Conditions
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_ODH
t_CNT
f_CNT
t_ACNT
f_ACNT
f_MAX
Array clock hold time
Array clock to output delay
C1 = 35 pF
Array clock high time
Array clock low time
Minimum pulse width for clear (2)
and preset
Output data hold time after
clock
C1 = 35 pF (3)
Minimum global clock period
Maximum internal global clock (4)
frequency
Minimum array clock period
Maximum internal array clock (4)
frequency
Maximum clock frequency
(5)
Speed Grade
Unit
-7
-10
-15
Min Max Min Max Min Max
1.8
3.0
4.0
ns
7.8
10.0
15.0 ns
3.0
4.0
6.0
ns
3.0
4.0
6.0
ns
3.0
4.0
6.0
ns
1.0
1.0
1.0
ns
8.0
10.0
13.0 ns
125.0
100.0
76.9
MHz
8.0
10.0
13.0 ns
125.0
100.0
76.9
MHz
166.7
125.0
100.0
MHz
Table 36. EPM7192S Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
t_IN
t_IO
t_FIN
t_SEXP
t_PEXP
t_LAD
t_LAC
t_IOE
t_OD1
t_OD2
t_OD3
t_ZX1
t_ZX2
t_ZX3
t_XZ
t_SU
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay C1 = 35 pF
Output buffer enable delay C1 = 35 pF (6)
Output buffer enable delay C1 = 35 pF
Output buffer disable delay C1 = 5 pF
Register setup time
Speed Grade
Unit
-7
-10
-15
Min Max Min Max Min Max
0.3
0.5
2.0 ns
0.3
0.5
2.0 ns
3.2
1.0
2.0 ns
4.2
5.0
8.0 ns
1.2
0.8
1.0 ns
3.1
5.0
6.0 ns
3.1
5.0
6.0 ns
0.9
2.0
3.0 ns
0.5
1.5
4.0 ns
1.0
2.0
5.0 ns
5.5
5.5
7.0 ns
4.0
5.0
6.0 ns
4.5
5.5
7.0 ns
9.0
9.0
10.0 ns
4.0
5.0
6.0 ns
1.1
2.0
4.0
ns
Altera Corporation
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