EPM7064LI44-15 Datasheet, PDF (48/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Table 34. EPM7160S Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-15
Min Max Min Max Min Max Min Max
t_CLR
Register clear time
t_PIA
PIA delay
(7)
t_LPA
Low-power adder
(8)
2.4
1.6
11.0
3.0
2.0
10.0
3.0
1.0
11.0
4.0 ns
2.0 ns
13.0 ns
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t_LPA parameter
must be added to this minimum width if the clear or reset signal incorporates the t_LAD parameter into the signal
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) The f_MAX values represent the highest frequency for pipelined data.
(6) Operating conditions: V_CCIO = 3.3 V ± 10% for commercial and industrial use.
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t_LPA parameter must be added to the t_LAD, t_LAC, t_IC, t_EN, t_SEXP, t_ACL, and t_CPPW parameters for macrocells
running in the low-power mode.
Tables 35 and 36 show the EPM7192S AC operating conditions.
Table 35. EPM7192S External Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
Input to non-registered output C1 = 35 pF
I/O input to non-registered
output
C1 = 35 pF
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay C1 = 35 pF
Global clock high time
Global clock low time
Array clock setup time
Speed Grade
Unit
-7
-10
-15
Min Max Min Max Min Max
7.5
10.0
15.0 ns
7.5
10.0
15.0 ns
4.1
7.0
11.0
ns
0.0
0.0
0.0
ns
3.0
3.0
3.0
ns
0.0
0.5
0.0
ns
4.7
5.0
8.0
ns
3.0
4.0
5.0
ns
3.0
4.0
5.0
ns
1.0
2.0
4.0
ns
48
Altera Corporation