EC7401QI Datasheet, PDF (42/44 Pages) Altera Corporation – 4-Phase PWM Controller with 8-Bit DAC Code

Page 42
0.6
0.4
0.2
I_L,P-P = 0
I_L,P-P = 0.5 I_O
I_L,P-P = 0.75 I_O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR SINGLE-PHASE CONVERTER
For a two phase design, use Figure 21 to determine the input-capacitor RMS current requirement given the duty cycle, maximum
sustained output current (I_O), and the ratio of the per-phase peak-to-peak inductor current (I_L,P-P) to I_O. Select a bulk capacitor with
a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated.
The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage.
Figures 22 and 23 provide the same input RMS current information for three and four phase designs respectively. Use the same
approach to selecting the bulk capacitor type and number as described above.
Low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling
edge voltage spikes. The result from the high current slew rates produced by the upper MOSFETs turn on and off. Select low ESL
ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitic impedances and
maximize suppression.
Multiphase RMS improvement
Figure 23 is provided as a reference to demonstrate the dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example, compare the input RMS current requirements of a two-phase converter
versus that of a single phase. Assume both converters have a duty cycle of 0.25, maximum sustained output current of 40A, and a
ratio of I_L,P-P to I_O of 0.5. The single phase converter would require 17.3A_RMS current capacity while the two-phase converter
would only require 10.9A_RMS. The advantages become even more pronounced when output current is increased and additional
phases are added to keep the component cost down relative to the single phase approach.
Layout Considerations
The following layout strategies are intended to minimize the impact of board parasitic impedances on converter performance and to
optimize the heat-dissipating capabilities of the printed-circuit board. These sections highlight some important practices which should
not be overlooked during the layout process.
Component Placement
Within the allotted implementation area, orient the switching components first. The switching components are the most critical
because they carry large amounts of energy and tend to generate high levels of noise. Switching component placement should take
into account power dissipation. Align the output inductors and MOSFETs such that space between the components is minimized
while creating the PHASE plane. Place the MOSFET driver IC as close as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement
of these components for each phase.
Next, place the input and output capacitors. Position one high-frequency ceramic input capacitor next to each upper MOSFET
drain. Place the bulk input capacitors as close to the upper MOSFET drains as dictated by the component size and dimensions.
Long distances between input capacitors and MOSFET drains result in too much trace inductance and a reduction in capacitor
performance. Locate the output capacitors between the inductors and the load, while keeping them in close proximity to the
microprocessor socket.
EC7401QI 4-Phase PWM Controller with 8-bit DAC Code
09614
March 14, 2014
March 2014 Altera Corporation
Rev A