EP4CGX30CF23C8N Datasheet, PDF (40/42 Pages) Altera Corporation – Cyclone IV Device Datasheet

1–40
Chapter 1: Cyclone IV Device Datasheet
Glossary
Table 1–46. Glossary (Part 4 of 5)
Letter
Term
t_C
Channel-to-
channel-skew
(TCCS)
t_cin
t_CO
t_cout
t_DUTY
t_FALL
t_H
Timing Unit
Interval (TUI)
t_INJITTER
t_{OUTJITTER_DEDCLK}
t_{OUTJITTER_IO}
t_pllcin
T
t_pllcout
Definitions
High-speed receiver and transmitter input and output clock period.
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the TCCS measurement.
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
Delay from the clock pad to the I/O output register.
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%).
Input register hold time.
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w).
Period jitter on the PLL clock input.
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards:
Transmitter
Output
Waveform
Single-Ended Waveform
V_OD
Vos
Positive Channel (p) = V_OH
Negative Channel (n) = V_OL
Ground
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V_OD
0V
V_OD
p-n
t_RISE
t_SU
U
—
Signal low-to-high transition time (20–80%).
Input register setup time.
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Cyclone IV Device Handbook,
Volume 3
December 2013 Altera Corporation