EP3C25E144I7 Datasheet, PDF (4/8 Pages) Altera Corporation – Cyclone III low-cost FPGAs

Features and benefits
You can turn ideas into revenue faster than
ever because we deliver numerous features and
benefits that help you lower your system and
development costs. Flexibility enables you to
keep up with fast-evolving standards easily.
Scalable digital signal processing (DSP) perfor-
mance and embedded memory let you increase
or enhance feature sets. All of this with the lowest
power consumption of any FPGA available
today. To top it off, we’re the lowest-cost FPGA
solution around. Choose Altera to win.
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Phase-locked loops
M9K memory blocks
Logic array
Embedded 18-bit x 18-bit
multipliers
Side I/O cells with support for
LVDS signals up to 875 Mbps
Top and bottom I/O cells for
memory interfaces up to 400 Mbps
Lowest-power
65-nm
FPGAs
• Manufactured using a low-power 65-nm process technology.
• Core static power as low as 35 mW at 25^oC junction temperature.
• Support for hot-socketing operation so unused I/O banks can be turned
off when there’s no current.
• Low-power benefits include: system thermal management, elimination
or reduction in cooling system costs, and extended battery life for
portable applications.
Cost optimized
for the
best value
anywhere
• Staggered I/O ring to reduce die size and board space.
• Selection of low-cost packages.
• Support for low-cost serial flash and commodity parallel flash configu-
ration devices.
• Cyclone series FPGAs are built from the ground up for low cost.
Complete
system
integration
• 1.7 times the density to 120,000 logic elements (LEs) and over 3.5 times
the embedded memory to 4 Mbits over Cyclone II FPGAs.
• 260-MHz multiplier performance with the highest multiplier-to-logic
ratio in the industry.
• Robust clock management and synthesis with dynamically reconfigu-
rable and flexible phase-locked loops (PLLs).
• Improved signal integrity with adjustable I/O slew rates.
• Support for high-speed external memory interfaces including DDR,
DDR2, SDR SDRAM, and QDRII SRAM with an autocalibrating PHY
for fast timing closure.
• Support for I/O standards including LVTTL, LVCMOS, SSTL, High-
Speed Transceiver Logic (HSTL), PCI Express, LVPECL, LVDS, mini-
LVDS, reduced swing differential signaling (RSDS), and point-to-point
differential signaling (PPDS).

Cyclone III FPGAs • March 2007 • www.altera.com