EPM7064SLC84-10 Datasheet, PDF (39/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This parameter applies to MAX 7000E devices only.
(3) This minimum pulse width for preset and clear applies for both global clear and array controls. The t_LPA parameter
must be added to this minimum width if the clear or reset signal incorporates the t_LAD parameter into the signal
path.
(4) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(5) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(6) The f_MAX values represent the highest frequency for pipelined data.
(7) Operating conditions: V_CCIO = 3.3 V ± 10% for commercial and industrial use.
(8) The t_LPA parameter must be added to the t_LAD, t_LAC, t_IC, t_EN, t_SEXP, t_ACL, and t_CPPW parameters for macrocells
running in the low-power mode.
Tables 27 and 28 show the EPM7032S AC operating conditions.
Table 27. EPM7032S External Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min Max Min Max Min Max Min Max
t_PD1
t_PD2
t_SU
t_H
t_FSU
t_FH
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_ODH
t_CNT
f_CNT
t_ACNT
Input to non-registered output C1 = 35 pF
5.0
6.0
7.5
10.0 ns
I/O input to non-registered
output
C1 = 35 pF
5.0
6.0
7.5
10.0 ns
Global clock setup time
2.9
4.0
5.0
7.0
ns
Global clock hold time
0.0
0.0
0.0
0.0
ns
Global clock setup time of fast
input
2.5
2.5
2.5
3.0
ns
Global clock hold time of fast
input
0.0
0.0
0.0
0.5
ns
Global clock to output delay C1 = 35 pF
3.2
3.5
4.3
5.0 ns
Global clock high time
2.0
2.5
3.0
4.0
ns
Global clock low time
2.0
2.5
3.0
4.0
ns
Array clock setup time
0.7
0.9
1.1
2.0
ns
Array clock hold time
1.8
2.1
2.7
3.0
ns
Array clock to output delay
C1 = 35 pF
5.4
6.6
8.2
10.0 ns
Array clock high time
2.5
2.5
3.0
4.0
ns
Array clock low time
2.5
2.5
3.0
4.0
ns
Minimum pulse width for clear (2)
and preset
2.5
2.5
3.0
4.0
ns
Output data hold time after
C1 = 35 pF (3) 1.0
1.0
1.0
1.0
ns
clock
Minimum global clock period
5.7
7.0
8.6
10.0 ns
Maximum internal global clock (4)
frequency
175.4
142.9
116.3
100.0
MHz
Minimum array clock period
5.7
7.0
8.6
10.0 ns
Altera Corporation
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