EPF6024AQC208-3N Datasheet, PDF (39/52 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 6000 Programmable Logic Device Family Data Sheet
Table 20. IOE Timing Microparameters Note (1)
Symbol
t_OD1
t_OD2
t_OD3
t_XZ
t_ZX1
t_ZX2
t_ZX3
t_IOE
t_IN
t_{IN_DELAY}
Parameter
Output buffer and pad delay, slow slew rate = off, V_CCIO = V_CCINT
Output buffer and pad delay, slow slew rate = off, V_CCIO = low voltage
Output buffer and pad delay, slow slew rate = on
Output buffer disable delay
Output buffer enable delay, slow slew rate = off, V_CCIO = V_CCINT
Output buffer enable delay, slow slew rate = off, V_CCIO = low voltage
IOE output buffer enable delay, slow slew rate = on
Output enable control delay
Input pad and buffer to FastTrack Interconnect delay
Input pad and buffer to FastTrack Interconnect delay with additional delay
turned on
Conditions
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
C1 = 5 pF
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
Table 21. Interconnect Timing Microparameters Note (1)
Symbol
t_LOCAL
t_ROW
t_COL
t_{DIN_D}
t_{DIN_C}
t_LEGLOBAL
t_LABCARRY
t_LABCASC
Parameter
LAB local interconnect delay
Row interconnect routing delay
Column interconnect routing delay
Dedicated input to LE data delay
Dedicated input to LE control delay
LE output to LE control via internally-generated global signal delay
Routing delay for the carry-out of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Conditions
(5)
(5)
(5)
(5)
Table 22. External Reference Timing Parameters
Symbol
t₁
t_DRR
Parameter
Register-to-register test pattern
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local
interconnects
Conditions
(6)
(7)
Altera Corporation
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